Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by siva_7517

  1. siva_7517

    Partial lifted wire bond

    Thanks for the reply. X-ray only will be conducted on the sample products. I would like electrical test method to see if the bond is lifted for all the units in production? example: the resistance of lifted wirebond will be high. ---------- Post added at 09:11 ---------- Previous post was at...
  2. siva_7517

    Partial lifted wire bond

    Is there any method to test MMIC chip (SOT package) for partially lifted wirebond from die using electrical test? Thanks.
  3. siva_7517

    How to establish the width of power ring around the chip core?

    Re: power ring width yup...i can open...
  4. siva_7517

    dynamic power calculation

    Hi there, I have generated a power report from design compiler which consist of dynamic power (cell internal power and Net switching power). How can I determine the toggle rate of my design from dynamic power ?
  5. siva_7517

    Nclaunch display error

    Hi there, When i trying to invoke nclaunch by : nclaunch & there is a error statement of : Application initialization failed : no display name and no $DISPLAY environment variable How to solve this problem? Thanks
  6. siva_7517

    property equivalence verification

    Hi there, Can i know what is property equivalence? From my basic understanding it is based on finete state machine verification...and the tools that are used are like Innologic, 0-in, Verix and blacktie. Can anyone share their knowledge on what is property equivalence..thanks.
  7. siva_7517

    Guide to using formulas and functions in Excel 2003

    When I click on the image, the same image should appear in the next worksheet. please refer attachment above. Im not sure wther I can use macro to make the function work.
  8. siva_7517

    front end silicon design, what is it?

    front end silicon design Hi guys, Can i know wat is front end silicon design?
  9. siva_7517

    Wat does (!==) Verilog operator mean?

    Hi, Wat does this verilog operator means (!==): example A !== B
  10. siva_7517

    verilog testbench book

    Hi guys, Is there any verilog testbench e-book available to download. Thanks for sharing..:) Siva
  11. siva_7517

    How to establish the width of power ring around the chip core?

    HI there , I would like to know how we decide the width of power ring around the chip core? Siva
  12. siva_7517

    Silicon validation on ASIC

    Hi there, I would like to know why we have to do silicon validation on ASIC chip? Is it to see the timing violation in the design? Siva
  13. siva_7517

    IC testing board/software?

    just a question, I have just packaged my chip...n going to test the chip soon. Is that possible if i use logic analyzer to give the input pattern to the chip. do u have any reading material that u r willing to share. Thanks in advance...your kind assistant is really appreciated siva
  14. siva_7517

    What is needed to test an ASIC chip with 76 IO pads?

    Hi there, I have successfully fabricated and packaged ASIC chip for FFT application. This chip has 76 IO pads. I would like to know wat is the test setup and equipments that are needed to test this chip. I need to generate and input pattern to the chip and the output will be in logic analyzer...
  15. siva_7517

    test setup for ASIC chip

    Hi there, I have successfully fabricated and packaged ASIC chip for FFT application. This chip has 76 IO pads. I would like to know wat is the test setup and equipments that are needed to test this chip. I need to generate and input pattern to the chip and the output will be in logic analyzer...
See more

Part and Inventory Search

Back
Top