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Re: RTOS + Web Server
No, I am starting with nothing.
Do I really need an OS, can I run a web server alone.
All I need is to connect my test set to a PC using TCPIP
and use web pages to configure the test to execute.
I am designing a tester that will use Web Pages for configuration.
It is using ARM9 AT91RM9200 microcontroller.
I need a solution that includes RTOS and Web Server integrated
in a single package. The simpler, the better.
Any suggestions?
Thank you
Re: what is assertion??
The following example shows the benefit of using assertion in addition to digital
simulation. Assertion uses a symbolic language to infer the rules applaying to
a design. Lets decribe the rules for a RAM interface using assertions:
1) CS must be active during READ or...
Re: VCXO digital tuning
ddt694 paper is helping. I just need to add a Low Pass Filter bethween the the DAC and the VCXO.
I will switch new questions to Analog Circuit Design forum.
Thanks,
I need a stable oscillator with digital tuning: 19.44 MHz +/- 100ppm. Since I am
not familiar with analog design: is it possible to use a digital to analog converter
and connect the DAC output to the Control Voltage pin of the VCXO. This way it
will be possible load a "digital" value in the...
I need a stable oscillator with digital tuning: 19.44 MHz +/- 100ppm. Since I am
not familiar with analog design: is it possible to use a digital to analog converter
and connect the DAC output to the Control Voltage pin of the VCXO. This way it
will be possible load a "digital" value in the DAC...
I also favor using a top level RTL file to put the I/O cells including input registers and output registers. I also instantiate the cells to make sure I get the right cell type and drive I need. This is good place also to put the cell placement constraints. I use a separate timing constraint...
Re: VHDL or Verilog
Verilog is going to be the winner, especially with the release of 2001
and SystemVerilog. Already, $ynopsys is giving indication that it
will support Verilog more than VHDL. All VHDL tool accept Verilog now,
which was not the case some time ago.
A good design process is to have two teams, one that designs the RTL code and one that designs the test cases at the top level (Component interface). Both teams use the hardware specification as a reference.
The design team make some validation at the block level to validate the basic...
Actually the verilog version will work as shown below, because "shift"
will start with all 'x', after eight zeros are shifted in the out will go HI
and stay HI forever.
The gate version will not work because the "shift" may contain any
value from 0 to 255. The result will be correct only when...
vb link with ethernet
My problem is to control a remote equipment throught an Ethernet link using Visual Basic.
I will like to write a command to a TX-Buffer and have this buffer sent automatically to a RX-Buffer in the remote equipment. The same scheme in the test equipment will send a...
modulo function in verilog
It is perfectly valid to write :
always @ ( negedge RESETN or posedge CLK ) begin
if ( !RESETN )
COUNT<= 0;
else
COUNT<= COUNT + 1;
end
This the implementation of synchronous counter with asynchromnous active-low reset.
It basically mean that the propagation delay through the gates and wirings used to build the FF are such that the data may change 200ps before the clock edge and still meet the hold time requirement.
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