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Recent content by sekapr

  1. S

    AMD is cutting 10% of workforce

    Semiconductor industry is facing lot of challenges. Profitability is the main concern. Five years from now there will not be any AMD. I am not against AMD. TI, AMD,NXP,ST,Freescale etc all these companies design great chips but make very less money, infact most of them loss making. As we moved...
  2. S

    Question about symbols for inverter in Cadence Tool

    Re: Cadence Tool Help copy to a different cellname and change
  3. S

    What does multicycle path mean?

    Re: Multicycle path all static timing analysis tools assumes by default the flop to flop data transfer takes one clock cycle. u need explictly mention as mcp if it takes more than one clock cycle.
  4. S

    65 nm Leakage Problem

    multi-vt and power gating is the technique widely used
  5. S

    predictive berkely transistor models

    back annotation spef, dspf annotate delays with parasitic delays
  6. S

    How to add a pulldown menu in ciw?

    it is very easy. check in the cadence manual
  7. S

    history of Cadence and Synopsis

    u will get company info on the respective websites
  8. S

    Several questions about doing floorplan

    Re: Reg: Floorplan apart from avoiding the stdcells placement near the ebbs, the halo also helps in maintaining the N-WELL spacing
  9. S

    confusion between latch and flipflop

    a latch is level triggered understanding the difference between latch and flop is critical for timing fix
  10. S

    The difference between instance and cell

    Re: Instance and cell cells are basic logic gates. Example. Say you have an inverter with drive strength 1X. You may be having thousands, lakhs of 1X inverters in your design. How will you differentiate them?. By naming it individually called instance names.
  11. S

    Learning VLSI at an institute

    Re: A query friends In which institute did u do vlsi courses?
  12. S

    Anyone have I2C Slave Verilog code?

    i2c in verilog opencores.org

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