how to find cell delay,net dalay,.....

[dsairajkiran]

In soc enocunter 5.2,how to know critical path ,gate dealy,input delay,output delay for a design.wchich file gives information about those?

what is index1,index2 in .lib file?what is the meaning of on chip variation(ocv)?


Thanks in advance,

 

[quan228228]

For "on chip variation" , we can refer to "PrimeTime" manual. This is one of the type of timing analysis.

 

[au_sun]

what is index1,index2 in .lib file?

The index1 and index2 of the liberty file indicates the input slew Vs output load,

Based up on these two index values, the cell propagation delay and its output transition time values are charcterised as Look-up table in the Liberty file.

 

[sowmya005]

u can refer to TIMING written by SACHIN SAPATNEKAR. In this the calculation of delay for interconnect, combinational ckt and sequential ckt is given very clearly.

 

[energeticdin]

Hi Sowmya,

Do u know the link for TIMING written by SACHIN SAPATNEKAR...
or u have any softcopy...
Plz upload it if u have....
or if possible send thro my yahoo id: energeticdin@yahoo.co.in

 

[onlymusic16]

Do a search on eda upload/download section.

 

[sekapr]

read synopsys pt manuals

 

[arun_prabu]

Hi Sowmya,

Do u know the link for TIMING written by SACHIN SAPATNEKAR...
or u have any softcopy...
Plz upload it if u have....
or if possible send thro my yahoo id: energeticdin(at)yahoo.co.in

**broken link removed**

 

[master_picengineer]

Hi all,

Could you please arun_prabu upload this doc here ?
Thanks.

 

[salma ali bakr]

I have the file and tried to upload it but it failed
If anyone needs it, give me your mail please to send it to you

 

[master_picengineer]

Here my Mail:
master_picengineer@yahoo.fr

Thanks in advance.

 

[funnynypd]

do test may clear up things.