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Hi,
I have problems using the DDR2 RAM on my XUPV5-LX110t Board. I generated it using MIG core generator (ISE 12.1 and also 12.3 recently) with VHDL sources.
1. I didnt succeed in simulating the core using the generated example design, because the ddr2 model only is available as a verilog file...
Hi,
Im using the XUPV5 Virtex-5 Board with Xilinx ISE 12.1. Within XPS I built up a system design where I instantiated a DDR2 SDRAM memory controller as a user IP-Core, which I created with MIG / core generator before. I connected all relevant ports with my user design and made all neccessary...
Hi,
Im using the Xilinx XUPV5-LX110t development board and Xilinx ISE 12.1.
I succussfully instantiated the memory controller with MIG and core generator. Now I'm not sure about the clocking of the controller. It has a sys_clk input and a clk200 clock. The connection of the 200MHz clock is...
hi,
can you be a bit more precise what you are looking for? there is no "Medical image recognition and compression device". there are lots of different imaging technologies in medicine. see Medical imaging - Wikipedia, the free encyclopedia
Depending on that, you can do many different processing...
as i wrote, the PC always receives data. with the delay, the data is correct, without delay, only the data length is wrong. the header is always right as it is built in the UDP Core where I dont have influence.
the first process is entered because I can see the right data (01010101) in...
Hi,
Im trying to send UDP datagrams from a FPGA (Virtex5) to a Windows XP PC. On the FPGA I use the UDP/IP Core from opencores.org. From there I send a fixed number of datagrams to the PC
On the PC I use a simple C application calling the socket function recvfrom() in a loop until all datagrams...
Hi,
I'm using the UDP/IP Core from opencores.org.
My problem is to realize a best effort transmission from the FPGA to the PC. In the following code snippet I have two processes to transmit constant data. The send process is sending as soon as the destination is ready (ctrl_tx_phase_on=1)...
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