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Hi,
I have written TCL file and extract instances for cones.
the source file has multiple modules having same instances. for example :
module or3_55(A, B, C, z);
CLKBUF1 drc(.A (n_4), .Y (z));
endmodule
module nand2_248(A, B, z);
CLKBUF1 drc(.A (n_1), .Y (z));
endmodule
module(2681...
Thanks
I understand what you meant to say. yes you are right, definitely it will not recognize the library cells as there is like "NAND2X1" instance not nand2.
secondly, I need to synthesis as I want to individual cone of the digital circuits. let say 10 outputs then I need 10 different cones...
Hi,
I have written tcl file for one simple circuit including library path which keep all instances.
my source file contain this line: assign out = (~a & b & c) + (a & ~b & c);
it synthesis fine by taking gates from library but when i do like this in source file: nand2 g1 (a, b, out1)...
Hi I am running simulation on ncveriolg through command prompt.
Actually, I want that verilog code should use my library cells.
The library are in the path "/home/sarfaraz.ahmed/techlib/FreePDK45/osu_soc/lib/source/signalstorm/files/gscl45nm.lib"
how I include this library in our verilog code...
Even, I used redirect commands on rc prompt but its create only empty file. It does not copy the instance on file. Please look into attachment.
how would I save these cells in a file ? even it creates "gates.rep" but only empty.
Thanks
Thanks.
Below is reply from cadence support .
"the problem are the non-SKILL PCells, for which Cadence offers no support. It can be guess that some shared libraries were not loaded during start of Virtuoso, Please ask your foundry, if the PDK has been installed correctly."
Isn't it any PDK...
Thanks.
Actually I want to see all instance which are fanin of my 1st output let say. It gives the result by the command :
rc:/> dc::all_fanin -to g118/B -only_cells
when this command run on terminal It lists all instances for example in that case it gives:
"/designs/FA/instances_comb/g118...
Hi,
can anyone help how to set Constraints of fanin and then save that cone ? actually, I traverse back from my output to input and I want to list all gates comes under that output cone ?
Is there any setting in tcl file then please share here. I below show the tcl file which i write but I...
Thank you.
I have already tried all these way like hierarchy, displayed levels and shift-F. Is it may be any licence issue ? As in attachment cds.log shows something like that.
can you please check that cds.log , may be there is some information which will help to understand the problem.
thanks
Thanks.
I checked, In display option settings are fine. It might be some path issue , but i couldn't find how I verify this.
If is there a way please suggest.
hello, I am facing one problem that My layout cmos cells are not showing their instances (gate, drain, source).It just shows empty boxes.
I tried Shift+F , stop level to 32, AV in LSW . but It's not working. I see my tech file is there but I don't know why it's not showing their instances . It...
How we set "assura_tech.lib" ? It is not in my project directory. due to which assura is not running. I read in somewhere that there is script, which fix it by itself.
can anyone help for this.
Thanks
Thank you.
I have checked, there is no such file in root ""assura_tech.lib". So how I fix this issue ?
It means Assura is not installed properly ? Now what should I do further to solve this problem ?
once again thanks for such kind of help.
Thanks.
I've done this already. but its not working. In schematic design it pick those library cells but when I design layout and assura it does not show that library "cmos150" instead it shows undefined.
Let me show you full snap. I am really upset to how to solve this issue.
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