synthesis tcl file though rc compiler

[sarfaraz.ahmed]

Hi,

I have written tcl file for one simple circuit including library path which keep all instances.
my source file contain this line: assign out = (~a & b & c) + (a & ~b & c);⁠⁠⁠⁠
it synthesis fine by taking gates from library but when i do like this in source file: nand2 g1 (a, b, out1); then it does not maps and shows warnings in rc compiler and does not maps. please attached find.


TCL file keep this info :
set_attribute lib_search_path /home/sarfaraz.ahmed/techlib/FreePDK45/osu_soc/lib/source/signalstorm/files/

## This defines the library to use
set_attribute library gscl45nm.lib

read_hdl /home/sarfaraz.ahmed/RC/test.v

what problems might be there ?

 

[ThisIsNotSam]

how do you expect the tool to map something called nand2 out of the blue? what if it was called zom23blang9? see what I mean? the name has to a verilog primitive or a REAL PROPER INSTANCE of a standard cell from the library

and most importantly, why are you trying to synthesise gate level logic?

 

[sarfaraz.ahmed]

Thanks

I understand what you meant to say. yes you are right, definitely it will not recognize the library cells as there is like "NAND2X1" instance not nand2.

secondly, I need to synthesis as I want to individual cone of the digital circuits. let say 10 outputs then I need 10 different cones of the circuit.
I am running actually some benchmarks of c432 ISCAS-85 circuits and these are in gate levels design. I write TCL to generate output nets of each respective cone.

also If I run the Verilog hierarchical behavioral model of this bench mark. it shows following warnings . please see an attachment.


Thanks