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Recent content by sarah23

  1. S

    ISE implementation clock error...?

    ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / has anybody seen such an error before ...i gets it when during implementation phase ...how to correct it any ideas...?
  2. S

    adressing with hyper terminal

    i am using 19200 buad-rate and have checked its output on hyper-termial ...its working ok u can take a look on my top-level module but when i intertace my hyper_terminal.txt code b/w two FIFOS it does't work ...!
  3. S

    adressing with hyper terminal

    buad rate is exactly f9 i hav configured it properly...u mentioned abt the clock in the hyperterminal.txt is this necessary ..?ok i will change it ...the fifo available in core generator do the same thing as my fifo does , imean they will input same amount of bits buffer them and same will be...
  4. S

    adressing with hyper terminal

    i am using spartan3 board...i send a character 'l' through hyper terminal ...uart_rx with fifo receives it on fpga and send that input data to this rom ...as a result the output 32 bit data does through fifo_tx to uart_tx and result should be shown on hyper terminal ..but it does not... now...
  5. S

    serial to parallel vs UART RX

    thanx 4 the info. , i got it serial to parallel / parallel converter operates on synchronous input output signals based on system clock.....but let say it if i make the inputs syn. to system clk then it will work isn't it ....? i can try it because i know terminal baud rate e.g 9600 bits/sec and...
  6. S

    adressing with hyper terminal

    im using hyper terminal to send addres to a rom so that particular output it shows ...i have done everything ...my coding is in verilog ...it shows perfect results with a simulator but with a hyper terminal its does not ....plx suggest me something ...im attaching my code with it
  7. S

    serial to parallel vs UART RX

    im using system generator 10.1 ....i use block serial to parallel converter that is i think equivalent to UART RX. ......... now i want to send data through hyper terminal and use those characters to run the next block....but those characters does't appear after serial to parallel conversion as...
  8. S

    vhdl syntax help needed

    vhdl: Add_next:hybadd port map(PC_out,(2 => '1',others => '0'),add_next_out); verilog converted: hybadd Add_next (PC_out, {2 : 1'b1, {a{1'b0}}}, add_next_out); i don't understand wat does this means (2 => '1',others => '0') <==> {2 : 1'b1, {a{1'b0}}}
  9. S

    design and verify the MIPS Single-cycle processor

    actually im working on the same project if u hav done it plz tell me how to simulate the MIPS n which tools?
  10. S

    tools for mips processor simulation ...!

    hey , i hav made my single cycle mips code in verilog HDL now i hav 2 check my processor for results...can u plz help me out abt what are the steps now ? n simulation tools required ...i don't know how 2 write assembly code 4 it plz. do provide some examples ...thanx
  11. S

    MIPS code in verilog HDL

    i hav got this MIPS code but when i synthesize this on Xilinx ise10.1 it give 0 eroors but alot of warnings abt ports that r not connected but i think all of perfectly connected ...can nybody figure it out where z the problem ...code is attached with it
  12. S

    MIPS code in verilog HDL

    thanx its really helping alot..!
  13. S

    MIPS code in verilog HDL

    can nyone tell me abt simple MIPS verilog code without pipeling ...n its implementation on fpga
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