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Hi,
I am designing a gain=1 negative charge pump using SC circuit. Whenever the switches are turning on/off, there will be certain amount of glitches at the output. We can try to slow down the transition to reduce the glitches, but it will also degrate the efficiency of the NCP. Is there any...
Hi,
I want to simulate the supply rejection of my regulator using PAC. The regulator is used to provide a clean "supply" for ring osillators in a PLL. This is only a standalone simulation containing only regulator, oscillators, and some bias circuits.
Since I am only interested in the harmonic...
Hi,
This is a famous PLL paper, and I just went back to check it out. I understand that the replica bias is used to dynamically adjust the bias current in accordance with supply variation. Therefore, the lower swing limit of the buffer stage is always equal to Vctrl. This is good. But the...
Thanks all for the replying! I don't have switching stages in my circuit. From the transient response, it looks fine. So it's most likely due to some weird software problem. In my simulation log, it shows "Finding DC approximate solution failed". But without a DC op, how can the simulator...
I am referring to open loop gain in my post. I put an "iprobe" instance in parallel with a 1GHz resistor in the feedback loop. Both are ideal devices only for simulation purpose. But I don't know what cause the sudden change of phase response. Magnitude response looks fine, only gradual variation.
Hi,
I am simulating the AC response of a unity-gain feedback amplifier using Spectre stb analysis. It works fine for most corners. But for some corners such as slow-fast(t=-40,125; vdda=2.05), the loop phase suddenly change to 0 degree at DC (it's supposed to be 180 degree). That means positive...
Thanks for your reply. I have a slightly different chip which is working fine. In that chip, the input and feedback paths have separate sampling circuits, but in this chip the two sampling circuits are combined. So, I am not quite sure whether it's related to the integrator's overflow problem...
This is a second-order modulator with feedback structure. From the measurement, it outputs a long series of 1 or 0 once a while, then it returns to normal operation...
Since it's only second-order, so it's supposed not to have stability problem. But what would cause this strange behavior...
Hi,
I am designing a 2nd order delta sigma modulator using CIFB structure. The supply voltage is 1.5V, and feedback reference is also 1.5V. If my differential input voltage peak is 1.6V, the in-band quantization noise level looks OK, but there are also very high harmonic tones. Then if I reduce...
Looks like if there is not the DFF, the output will enter a limited-cycle osicllation? I am not sure how to express that meaning in a formal language. Thanks
Edward
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