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in VHDL for the signals the driver is created which assign the values at the scheduled time
but for the variables no such drivers are created.
the values to the variable are assigned without any delta delay but for the signals the values are always assigned after the delta delay if no delay is...
Re: FFs with Negedge!!!
For the negative edge triggered FFs all the timing parameters are measured with reference to the falling edge or the negative edge of the clock
pipelining and parallelism
parallelism means we are using more hardware for the executing the desired task. in parallel computing more than one processors are running in parallel. there may be some dedicated hardware running in parallel for doing the specific task.
while the pipelining is an...
Re: Synthesis
hi
Basic need for the synthesis is synthesis tools. there are many levels in the vlsi design like RTL, Gate Level, Circuit Level, etc. u have tool at each level for the synthesis. if u want the synthesis of ur VHDL code than u must need to ensure that ur code is synthesisable...
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