What is the basic things you need for doing synthesis in VHDL?

[sachin maheshwari]

hi
wat is the basic need for doing synthesis.(VHDL)

 

[bigrice911]

Synthesis

basic need is to have a synthesis tool. you have many choices!

 

[tosonal.jain]

Re: Synthesis

hi
wat is the basic need for doing synthesis.(VHDL)

hello
U see Synthesis provides u with the HArdware which u wil get after Coding. Its the Actual HArdware description of ur RTL.

For this we hav many synthesis tools like Leonardo spectrum and many others likewise.

 

[zhangpengyu]

Synthesis

clock relative and rst.
timing.

 

[vinodkumar]

Re: Synthesis

hi
if you see vlsi design cycle,first we will define problem with some constraints,to tht we write formal description using VHDl or verilog.the written code can be used to do simulation(functional verification).,but the need is vlsi designer should provide HW.tht can be done when we do synthesis for the code written using synthesizer.

the output file of a synthesizer is a netlist consists of components and their interconnections,the component are assigned,schduled and mapped based on the code written.

important thing to note is dont expect synthesis tool to provide an optimum netlist for a worst code written.

bye find more frm other texts in the board.

 

[sanjay298]

Re: Synthesis

hi

Basic need for the synthesis is synthesis tools. there are many levels in the vlsi design like RTL, Gate Level, Circuit Level, etc. u have tool at each level for the synthesis. if u want the synthesis of ur VHDL code than u must need to ensure that ur code is synthesisable because all the vhdl statements are not synthesisable. Initially the vhdl was created as a testing and verification languages. Later the pepole/designers started to use the language for the simuation and synthesis. U must also avoid the latches in the synthesis.

 

[nandhika]

Synthesis

hi,

Basic need for doing synthesis is to get a netlist (Gate level) from the code.

 

[lever]

Re: Synthesis

you must design the netlist (like VHDL)
And you must have the synthesis tool. It can not be waived.
Of course, you need have the ability to use the tool

hi
wat is the basic need for doing synthesis.(VHDL)