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Recent content by sakthikumaran87

  1. S

    USB3 enumerated as USB2! Pl Help

    Hi All, I am working on a USB host capable of 3.0 speed. When i connect a 3.0 pendrive, Linux in my board detects it as USB2.0 and not as USB3.0. Any pointers on what to check or how to debug? Thanks in Advance!
  2. S

    Clock Domain Crossing!

    It was an interview question to my friend, so couldnt provide more details.. the question itself is on how to design the interface to propagate signals between two black boxes of unknown freq. ...
  3. S

    Clock Domain Crossing!

    Hi All, I have a design related question on CDC. I have two black boxes working async. to each other and i am not aware of both the clk speed. Is it feasible to insert a sync. for the data / ctrl signal that is needed to pass data properly between the two black boxes. I need to design such...
  4. S

    I2C Read Doubt!! Pl clarify!

    Hi All, I am following Phillips I2C spec, and in that they have given that a read will happen only after a dummy write to that address, whereas write can be directly done to the address. Why is this? Why cant we directly read from a reg without making a dummy write to it. is this protocol...
  5. S

    Question on Chip Architecture!!

    oh ok thanks for your input.
  6. S

    Question on Chip Architecture!!

    Hi Experts, Am trying to understand the general chip Architecture. I have a very basic question. In the chip, we give a base address to all the attached components. For ex. assume i am giving the addr 0x4000 to I2C block, then i can access the I2C registers using the base addr from CPU. I am...
  7. S

    RTL for synthesis for loops

    For loop is the only synthesize loop, but it is always wise not to use loops in Verilog as timing closure will be an issue.
  8. S

    WRITE ONCE type registers

    How about using OTP??? It's guess. Am nt very sure. Others can correct me if wrong
  9. S

    Timing Doubts!! Need Claricfication

    Hi, 1. Negative hold time means that the hold value is very small and in real cases will be assumed to be zero. 2. The negative hold time should be good as if there are hold delay in final chip it will becoma a garbage. And having negative hold may have sifde effects like lowering freq of...
  10. S

    what are the issues in Backend if we use assign statements in netlist ?

    i dont think there will be any.
  11. S

    Setup/Hold scenario when pos edge launch flipflop - neg edge capture flipflop

    hi Guys, Nice discussion. Actually when you say Hold violation, it means the same clk cycle will be verified. And here you are launching in +ve edge and you are capturing in -ve edge, but the hold check will be done wrt to 2 +ve clk cycles and hence we arrive at a half cycle additional margin...
  12. S

    Doubt in SATA PHY BIST Mode !

    Hi any inputs??
  13. S

    Doubt in SATA PHY BIST Mode !

    Hi All, i am validating a SATA Host. I need to know, when we say a near end loopback(meaning the tx and rx of the transmitter is connected without a device), whether the loopback happens in analog region or digital region. If analog where is it actually happening and which peripherals will take...
  14. S

    Need Help In Validation!

    Hi, I am a fresher in SOC Validation, and it would be very helpfull if anyone of you can share me any PPTs, PDFs, Books or methodologies on Si Validation. Thanks in Advance
  15. S

    FSM in Verilog problem: why leds don't light up?

    Brother, the clock is an output of a module instantiated. So try to find whether the clock is generated properly in the ddr_interface module.
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