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INCISIVE SIMULATOR
Hi
It should come with ur tool installation.
5.8 is an older version.
u can also find it through cadence website.
u need to register to access docs in cadence.
best of luck
Regards
Srinivas
modelsim compile sdf file
seems like u r using a student version of modelsim...
the timescale directive is different in ur testbench and in ur netlist file.
just add the correct timescale in ur top level file tat u simulate(ur tb top) and it should apply to the leaf levels also unless they are...
Re: Denali question
Hi,
denali soma file takes an initialization file which has the format something like this...
the above thing fills the whole memory with 0xff.
u can give individual address with the respective values...
the initialization file has to be included in ur top rtl file as a...
design compiler naming rule
Yes synopsys does this.
If u see from the code(Verilog netlist) the output of ur FF(Q) will somewhere connected to ur output and say ur output signal names is "opt". name "opt" will not be changed. as ur Q output ,if it is connected to say opt then the wire n2214...
interfacing RAMs
all of them have the same bus definitions
only the data width changes....
i still dont understand wat do u mean by universal method......
Thanks and Regards
Srinivas
yes u r right.
u may use all the tools from a single EDA vendor(if he supports all the tools in the flow) but the problem is how efficient is each tool in part of the flow depends...
For example
when u do simulations u have cadence nc sim which is faster in case of netlist simulations compared...
Bottom up synthesis is done so that u can characterise ur design and derive the constraints from the design.
But the final compilation with the derived constraints is Top down!!!!!
The Ultra mode supports inbuilt efficient library functions(like adders muls etc) and has a better algo to...
verilog doubt
you should get an 'x' in simulation because of the multiple drivers from both the modules driving ur top module.
Better to have control at the top level as suggested earlier.
system verilog/e
its system verilog
but as of now e shares a better market share due to the fact that most of the tools doesnt completely support system verilog.
Once system verilog is supported by all the tools system verilog dominates...
Need ur help on this
Ya tat sounds gud but as i havent touched the board which i have got long back, i need to get the basic setup working.
i need to measure the output quality without my processing unit and compare the output with my processing unit.
Ideally i should have some improvement...
Need ur help on this
I felt i need to get some basic confidence before is start to implement my Audio processing core in the fpga that sits inbetween the ADC and the DAC.
This is the initial set up which i need to make up and running....
Its a HW-SPAR3E-SK Xilinx kit
**broken link removed**...
to_unsigned with two arguments vhdl
U havent quantized ur design in Matlab
check the filter design user guide
after u design a filter u have to quantize it to fixed point so tat u can genrate ur synthesizable HDL.
Regards
Hi guys,
I have a small appliaction to be done.
kindly put in ur comments.
I need to capture an analog signal output through the audio jack from a pc(say from the headphones port) and feed it to the ADC of the spartan 3e board. i will capture the samples in a ram and read them back to route it...
report timing loop synthesis
Yes it should be the mux creating the problem.
Timing loops are to be essentially taken care in the RTL.
i faced an issue in which DC removed the timing loops but the same code when mapped to an FPGA couldnt tackle the issue.
I suggest you to better report the...
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