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I have a question.
I know Iss as a Current Source is only for ideal situation bcus it has infinite impedance so infinite CMRR value.
and if I use NMOS as a Current Source, it has a finite impedance so would have less CMRR value.
Are there any other features like advantages, disadvantages when I...
Okay so, I could set all the mosfets Saturation and get 29dB voltage gain in tran analysis.
But I have some questions.
1. AC(left one) and tran(right one) analysis in this circuit, they have different voltage gain. In Tran Analysis I could get 29dB voltage gain(Upper ones are output nodes...
Hello guys.
I would like to get more than 15dB in this circuit.
I set M3, M4, M5 as the same width and control M1, M2 width and Iss bias current.
I set the length all the same as 0.18um.
Am I doing in the right way? or can you tell me how to start with?
I use Hspice program
Mosfet model is TSMC...
Thank you so much.
sorry since I'm a student and I have no experience of designing circuit so I have a lot of questions.
Is there any tips setting the bias voltage, Vbiasp and Vbiasn?
Thank you for answering.
I have one more question.
Is it okay to have different width in cascode? I mean like for example, different width of NMOS M2 : L=0.18u W=50u // M3 : L=0.18u W=100u
I want to make this circuit having more than 30dB voltage gain by controlling Length and width of the mosfets and biasing Vgs.
But literally I have no idea how to start with this.
Can you guys pls give me some useful tips?
+the mosfet is TSMC 180nm level 49.
+Vdd is 2.5v
+1.8um < L < 5um
+...
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