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Recent content by Rocketmagnet

  1. R

    Verilog to detect double rising edge

    Got it. Right, makes sense. Thanks.
  2. R

    Verilog to detect double rising edge

    Yes, EDGES is asynchronous to CLK. Can you explain more about what you mean by double registering?A google search for verilog double registering didn't seem to return any relevant results.
  3. R

    Verilog to detect double rising edge

    I think I managed to do it with a counter in the end. Here's the code: module CS_Detect ( CS, CLK, EDGES ); output CS; input CLK; input EDGES; reg edges_reg; reg [3:0] Counter; reg CS; wire pos_pulse = EDGES & !edges_reg; wire neg_pulse = !EDGES & edges_reg; always...
  4. R

    Verilog to detect double rising edge

    Haha! It works! Thanks guys, you have been very helpful, and I have learned a lot with my first verilog project. There was only one problem, which is that the synthesiser didn't like the initalisation of edges_reg, so I left it uninitialised. I think I will try to modify it use a counter...
  5. R

    Verilog to detect double rising edge

    That's a good point. Fortunately, it's not super critical. Anything outside the spec can cause undefined behaviour (as long as it doesn't start WWIII). This function only really needs to distinguish between two types of event: a double rising edge, and a single rising edge. The double rising...
  6. R

    Verilog to detect double rising edge

    Aah, yes. Sorry. I missed that. I'm sure it has: Rule 1: Whenever a falling edge is seen, the output goes high. Rule 2: Whenever a rising edge is seen, if another rising edge was also seen no more than 15 clock cycles previously, then the output goes low. P.S. Did you look at the attached...
  7. R

    Verilog to detect double rising edge

    Hi, thanks for the new code. Isn't there a chance here that train will always be 0x01 during the last if statement? The problem I see with this approach is that a valid train looks like: * 0001111110000000 and an invalid train looks like: * 1111111110000000 So to be valid: * train must be...
  8. R

    Verilog to detect double rising edge

    That is correct, my code synthesises, but does not function according to spec. No. There is code there to detect both types of edge. See the "// CS Falling" and "// CS Rising" comments. To me is seems wrong because it only seems to be sensitive to the first two rising edges ever, not to all...
  9. R

    Verilog to detect double rising edge

    On closer examination, this code cannot be correct. always @(posedge clk) edges_reg <= {edges[0],edges}; // just store input, shift-in reg I assume you meant: always @(posedge clk) edges_reg <= {edges_reg[0],edges}; // just store input, shift-in reg Furthermore, the Counter is...
  10. R

    Verilog to detect double rising edge

    That's right. It's only on a rising edge that I'm interested in the time. On a falling edge, CS should always go high. As a beginner, I'm still not sure how to initialise the values. That's another thing I don't fully understand. I get the general idea, but I'm not exactly sure which I should...
  11. R

    Verilog to detect double rising edge

    Hi all, I am writing my first Verilog program, but I'm finding it quite hard. I just don't understand why it doesn't do what I expect. Can anyone critique this for me, many thanks. I would really like to get to know Verilog better, so I can write my own peripherals for the Cypress PSoC. The...
  12. R

    About Torque in DC gear motor.

    Plus the rolling resistance, which is a linear function of the weight of the robot. If the robot is driving on a flat surface, then this will be the only factor. You can measure the rolling resistance by disconnecting the motor, and putting the robot on an angled surface. The rolling...
  13. R

    Altium Designer pin-swapping between pins in different parts?

    There is one way, but it's not very lovely. Make a single component (both the symbol and the footprint) which consists of all of the resistors. Of course, this can only work if you can decide beforehand where on the board they will all go. This might also be annoying when creating the BOM and...
  14. R

    Suggest me a cheap camera module with jpeg compression

    Re: Cheap camera module? markus_e, Do you still have some of these cameras available? Hugo
  15. R

    5 x 8MSPS video into a PC

    Hi all, I have a problem: I've got five tiny CMOS image sensors (2mm x 2mm), each in a small space (about 10mm x 15mm). They take a clock signal in, and output an analog signal, requiring an 8MSPS ADC each. Somehow I need to get the image data into a PC. This is difficult because of the tight...
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