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Recent content by riddhi.kapasi

  1. R

    Clock rule violation: C5 and C8, need help!

    No one has any information about these violations?
  2. R

    Clock rule violation: C5 and C8, need help!

    I am trying to insert scan in my design. I am getting these 2 violation: Level sensitive port captured data affected by new capture violations (C5) Level sensitive port clock path affected by new capture violations (C8) What is the method to get rid of them? If anyone had smiliar violation...
  3. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    skal81 - Thnks for the help, did add clarity to the subject. I found this article about multi clock domain incase anyone's looking for clarity about the same: **broken link removed**
  4. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    Hi skal81, Could you explain why is it better to have one scan clock for scan? I have read this in many docs but dont get the understanding behind it. You mentioned it is better for coverage and CTS layout, can you elaborate or supply with some docs which explain the same. Thanks
  5. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    I have tried 2 scan clocks and could get rid of violation. Will try with only 1 scan clock and get back to you guys if any problems. Thanks for the help!
  6. R

    0 internal test pattern generated after insert_dft using DC

    I think I got the answer to my Q. Thanks anyways!
  7. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    There are no derived clocks. ck and ck_x2 are the 2 clock ports for my design. So does create_clock -period 80 -name clk -waveform {0 40} [ck ck_x2] means: creating a clock port clk and connect it with design clock ports ck and ck_x2? and does set_dft_signal -view existing_dft \ -type...
  8. R

    0 internal test pattern generated after insert_dft using DC

    I tried to insert scan in my rtl. My dft_drc report shows: Pattern Summary Report ----------------------------------------------- #internal patterns 0 ----------------------------------------------- Uncollapsed Stuck Fault Summary Report...
  9. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    Some help will be appreciated.
  10. R

    How to handle multiple clock domain while inserting SCAN using DFT compiler

    I am trying to insert SCAN in a design with 2 clock(ck, ck_x2)domains in following way: create_clock -period 80 -name clk -waveform {0 40} [ck ck_x2] set_input_delay -clock clk 2.0 [get_ports "*" -filter {@port_direction == in}] set_dft_signal -view existing_dft \ -type ScanClock...
  11. R

    Verilog HDL Synthesis A Practical Primer

    Re: verilog hdl synthesis a practical primer Thanks, indeed a good book!
  12. R

    suggest a book for digital electronics

    Hi, Can anyone mail me following ebooks : 1) Digital electronics by Morris Mano 2) byFloyd. email address : riddhi.kapasi@gmail.com Thanks in advance
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