How to handle multiple clock domain while inserting SCAN using DFT compiler

[riddhi.kapasi]

I am trying to insert SCAN in a design with 2 clock(ck, ck_x2)domains in following way:

create_clock -period 80 -name clk -waveform {0 40} [ck ck_x2]
set_input_delay -clock clk 2.0 [get_ports "*" -filter {@port_direction == in}]

set_dft_signal -view existing_dft \
-type ScanClock -timing [list 45 55] \
-internal_clocks none \
-port clk

My understanding is create_clock creates a clock port "clk" and connect it to souce_clock port ck and ck_x2 present in the design.
set_dft_signal uses this existing port "clk", since it is declared as ScanClock, tool can control all flops controlled by it (clk) and thus by ck and ck_x2

But when I run DFT_DRC, tool gives me violation warning:
Uncontrollable clock input of flip-flop violations (D1)

Please help me understand how can I handle multiple clock domain.

 

[riddhi.kapasi]

Some help will be appreciated.

 

[kornukhin]

If ck and ck_x2 aren't primary inputs dft_drc will not violate after 'insert_dft' with using AutoFix, but will still violate before it.
Are you sure you don't have any derived clocks?

 

[riddhi.kapasi]

There are no derived clocks.
ck and ck_x2 are the 2 clock ports for my design.

So does create_clock -period 80 -name clk -waveform {0 40} [ck ck_x2] means:
creating a clock port clk and connect it with design clock ports ck and ck_x2?

and does
set_dft_signal -view existing_dft \
-type ScanClock -timing[list 45 55] \
-port clk
means the created clk port is not being declared as ScanClock.

Thus whn clk is controlled, all the flops controlled by ck and ck_x2 are being controlled?
I am asking this as to knw if my understanding is correct.

 

[kornukhin]

"So does create_clock -period 80 -name clk -waveform {0 40} [ck ck_x2] means:
creating a clock port clk and connect it with design clock ports ck and ck_x2?"
- No, it creates clock waveform named "clk" on primary inputs ck and ck_x2. It doesn't create port 'clk'.

You should use:
set_dft_signal -type ScanClock -port ck...
set_dft_signal -type ScanClock -port ck_x2...
To set this ports as scan ports for DFT. After that flip-flop clock inputs will be controlled.

 

[skal81]

If I were you, I would try using a single clock for scan.
The common way is to insert a MUX on each clock with selection done by SCAN_MODE signal. For scan mode, you use the same clock (which is from either a special port, or a port common with another one).
This helps for coverage, and also for CTS at layout.

 

[riddhi.kapasi]

I have tried 2 scan clocks and could get rid of violation.

Will try with only 1 scan clock and get back to you guys if any problems.

Thanks for the help!

 

[riddhi.kapasi]

Hi skal81,

Could you explain why is it better to have one scan clock for scan?
I have read this in many docs but dont get the understanding behind it.
You mentioned it is better for coverage and CTS layout, can you elaborate or supply with some docs which explain the same.

Thanks

 

[skal81]

> To riddhi.kapasi
I'm sorry I don't have docs explaining that, but from experience:
- using only one clock for scan allows to avoid clock domains crossing for scan. Clock crossing can be generated by the ATPG tools, but make analysis more complicated when facing a problem.
- you don't have to worry about the tester. Some tester (especially the old ones) support only a limited number of different clocks (number of generator is limited).
- during CTS, optimization is faster and easier (means you'll get better results) with few clocks. For normal operation you probably need several clocks, so it might not be necessary to increase the number of scan clocks. Some tools (for eg. Aprisa) use parallel optimization. So it's better to try to reduce the clock number when possible.
One clock for scan is not a "must", but I would say it makes design easier.
On the other hand I agree that using several clock also have advantages. Especially if you use at-speed test (it's becoming a must for high integration SoC using nanometer process).
Hopes it answer some of your questions.

 

[riddhi.kapasi]

skal81 - Thnks for the help, did add clarity to the subject.

I found this article about multi clock domain incase anyone's looking for clarity about the same:
**broken link removed**