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Recent content by rama_bing

  1. R

    shared library in verilog/systemc simulators

    We use shared(.so) files instead of compiling .cpp files everytime. Similarly, can we use .so files for some verilog modules which we do not change frequently? Thnks
  2. R

    noimmedca switch fo Questasim

    noimmedca switch for Questasim Hi all, Can anyone give example usage for "-noimmedca" switch for Questasim. I referred tool docs for this switch but I could not find any example.. thank you
  3. R

    [SOLVED] Interfacing a Monochrome LCD for Output of a Digital Circuit

    Re: Interfacing a Monochrome LCD for Output of a Digital Cir Hi, I hope following link will help you http://www.dinceraydin.com/lcd/index.html
  4. R

    Job for fresher’s in VLSI

    anywhere in asia, europe and america
  5. R

    Post-Layout Simulation - Glitching Probelm

    what about the clock skew at the flop inputs? if the flops are getting clock at different time instances, outputs of flops also changes at different time instances(which can cause glitch) please correct me if i am wrong..
  6. R

    can you explain to me the behavior of isolation cell?

    Hi Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'...
  7. R

    low power technics in rtl synthesis

    Hi, you can get UPF documentation from the following link http://www.accellera.org/activities/p1801_upf for upf topics: http://synopsysoc.org/magicbluesmoke/
  8. R

    how ESL effects current functional verification methods?

    Re: ESL and Verification Hi thank you for your reply my question is if 1.ESL to RTL(using some tool) is possible 2.formal verification between esl and rtl is also possible.. then functional verification will happen at ESL level by the designer(not at RTL level). That means.. there will not be...
  9. R

    how ESL effects current functional verification methods?

    ESL and Verification Hi, Does any one have idea about how ESL effects current functional verification methods (vmm,ovm etc) thank you
  10. R

    Effect of high level synthesis on verification.

    These days High Level Synthesis tools (Mentor's Catapult,Synfora's Pico for C/C++ to RTL) getting into industry. Will there be any effect of these tools on functional verification using VMM/OVM? (atleast in near future..) Please correct me if my question itself is wrong...
  11. R

    time scale selection in verilog

    Thank you for your reply. I feel we need precision only for the post layout simulations with SDF annotation(Please correct me if i am wrong). Are there any other situations in which precision is important ? What factors we must consider while selecting the timescale for simulation? Thank you..
  12. R

    time scale selection in verilog

    How to select timescale (time unit/time precision) for a given design? Thank you.
  13. R

    design for corner cases - how to decide the optimum margin?

    Re: design for corner cases Is there any mistake in my question?
  14. R

    design for corner cases - how to decide the optimum margin?

    design for corner cases i am new to analog design. i want to design a circuit which works at all corners. i am designing circuit with some margin ( design amplifier for 60db gain, if the spec is 50dB). Is there any way to decide the optimum margin for a spec based on the technology and circuit...
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