shared library in verilog/systemc simulators

[rama_bing]

We use shared(.so) files instead of compiling .cpp files everytime.
Similarly, can we use .so files for some verilog modules which we do not change frequently?
Thnks

 

[dave_59]

To some extent you can, depending on which simulator you are using. A big problem for large designs is that simulators want to perform global optimizations on all modules in a simulation to minimize the overhead of a signal crossing a module port boundary. For example, the simulator would like to collapse all the always @(posedge clk) blocks in all the modules into a single process instead of having to schedule hundreds of separate process.

Our simulator lets you compile modules into libraries, as well as optimize large chunks of your design into optimized units to save you the time of optimizing it over and over.