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Dear forumites,
could some one share more information about comparators to be used with ADC's and also can some one share information about the comparator type attached with this queiry.
raags
Verilog-A modelling
Dear friends,
I am working on a modelling project using a verilog-A and in particular working on an folded cascode OTA(sinle ended), Can some one help me with some inputs to set gain, PM, bias current , PSRR, slew rate.
And also can some one clarify me...
ADC accuracy
Dear members,
i am designing an ADC with onchip voltage refence to improve the accuracy. I have tried implementing a voltage reference which is to be used for ADC, but found to be having very bad load regulation. Can any one suggest me some way to implement a onchip voltage...
Re: Analog Switch
hi i am uploading the setup of on resistnace measurement, in which Vbias=xuvolts and vin is swept between 0 to VDD, So can you tell me how to measure Ron in this case.
cheers
raags
Re: Analog Switch
hi,
The switch comprises of two TG , an inverter for control and a pulldown transistor. The setup provided to us is, a bias voltage connected to input pin, input voltage source which need to be varied. So is that we should measure current at out and vout at outpin to...
hi every one,
Can any one tell me how to measure ON resistance of an Analog swicth for A/D analog input using Hspice. Infact i am designing a anlog switch, the client needs the ON resistnce values for different VDD( varying different VDD values). Also how to plot ON resistnace...
Hi rao,
baically you are having two different operating systems with which Tanner and dracula works.
Theoritically it is not possibel to interface cross platform softwares. If it is simpe windows application, it can run in linux using WINE utility. But tanner being a EDA tool it is...
hi every one i am using ultrasim for my circuit simulation. But the problem i have faced is that i cannot run DC simulations using ultrasim. Can anyone provide some info in this regard.
regards
raags
Hi every one i am designing a BGR for low power specifications, which uses a high gain opamp. I am not so sure how to design a BIAS circuit for opamp to generate a current of 3uA.SO if any one can give me details or design method how to design a bias ckt it will be a great help............
TIA...
hi everyone i am doing a BGR design where in i am planning to use the trimming resistor to overcome the process variation. I have decided to use 5bit trimming for resistor, but i have no clue how to prepare trimming resistor schematic for 5 bit combination . Prof baker has given a trimming...
hi every one , i am designinig a BGR for sub-1-v range and low power. I have no clue how to choose the required collector current to drive the PNP device in PTAT loop. Also if anyone can tell me how do i choose the reference current to start with, it will be of great use for me.
TIA
raags
hi Blackuni,
i am designing a BGR to generate a voltage about 0.6volts. I have finalised an architecture which is used for sub-1-v BGR without low Vth transistors and resisitive divide network. But my confusion is that how to size the BGR, like emitter are, base area or else. Also How...
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