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Hello, can anybody share me analog design signoff checklist?
For example, in digital design, it will be
1. functional: test regression passing rate; coverage; etc...
2. Timing: STA; postsim; etc...
...
In analog field, in the real tape-out signoff flow, is there any similar checklist?
Thanks,
Does anybody know how to how to distinguish violation type (setup/hold violation) in RC timing report?
In DC report, it can be showed by max and min. In RC report, which place will show this information?
Thanks
scanning flip flop
Question 1 is still NOT solved!!!
I checked spf file. Timing section and waveform table exsits.
I read synopsys document and found following sentence:
"after insert_dft, the initialization sequence is lost. You must reapply the same initialization sequence to ensure that...
scan flipflop
Dear dr_dft,
3. set_test_hold value for asynch. rst_b signal is ignored from the beginning creating protocol to the last dft_drc after insert_dft.
I tried as you said, removing set_test_hold for rst_b. The result of rerun is the new script produced the same result!!! And this...
I read the netlist after scan insertion. But I found in scan mode, comb logics are bypassed. All scan cells are connected with each other directly.
Is it right? If right, how can internal scan methodology find those defects in comb logic part?
Thanks a lot!
scan chain insertion
Hi, I tried a test for muxed flip-flop scan chain insertion, but I met a DRC violation as following:
Warning: Input force of chain c0 must be loaded by first cocking of in_reg1_reg (S6-1)
1 Invaild force scan input time violation.
This DRC violation ocurred after...
strobe before clock strobe after clock dft
dr_dft, I got the 1st question's answer from you reply. Thanks a lot, first.
Then about my 3rd question, I don't understand why strobe-after-clock protocol consist of following steps?
data scan in -> parallel measure cycle -> parallel capture cycle->...
Hi, dr_dft, I need you more.
----------------------------------------------------------------------------------------------
scan-in -> NFF1 -> NFF2 -> ... -> NFFn -> PFF1 -> PFF2 -> .. -> PFFm -> scan-out
If you reverse the order (posedge before negedge), you will find that at the boundary...
Synopsys document said,
For edge-sensitive scan shift style in mixed phases design( posedge and negedge sensitive register co-existing),
" for a positive pulse, the rising-edge-triggered filp-flop must be clocked first; for a negative pulse, the rising-edge-triggered flip-flop must be clocked...
types of protocol
I don't understand test protocol types in synopsys document.
1. How to distinguish "strobe-before-clock" protocol and "strobe-after-clock"?
For a consecutive clock, should we say point A is before-clock or after-clock?
1 2
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synopsys memory bist
Can anybody share his synopsys memory bist insertion flow?
Synopsys has many tools relate to DFT insertion, such as DC, DFT compiler, BSD compiler, SocBist deterministic logic bist generator, TetraMAX ATPG generator and so on.
So if I want to do memory bist insertion...
Have anybody used Cadence's ICT platform?
When I use ICT for coverage, ncsim shows "*W,RNQUIE: Simulation is complete" at the moment it comes to run command but no simulation is run.
What does *W,RNQUIE mean? And what may be the possible reasons for it?
Thanks a lot!
testing for Analog part
Does anybody know how to test analog part on a tester? Also use something like ATPG? What would their test pattern?
Thanks a lot!
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