test protocol types - dft compiler

[qjlsy]

types of protocol

I don't understand test protocol types in synopsys document.

1. How to distinguish "strobe-before-clock" protocol and "strobe-after-clock"?

For a consecutive clock, should we say point A is before-clock or after-clock?

1 2
__ __
...__| |__| |__...
A

For cycle 1, point A is after-clock, but for cycle 2, it is before-clock.

If it is said the start phase of clock signal is the key, how could designer make sure that the start phase of real application can meet his assumption exactly, no matter it is from pll or external crystal oscillator?

2. For these two protocols, the instruction steps are different. What cause such differences? Why does the reason cause these two different instruction sequence but not others?

3. ATPG default chooses before-clock protocol. If semiconductor vendor specifies other strobe timing information, designer still could use ATPG to generate patterns, but need use the user's test protocol to guide ATPG, right?

Thanks a lot!

 

[dr_dft]

dft test protocol

I don't understand test protocol types in synopsys document.

1. How to distinguish "strobe-before-clock" protocol and "strobe-after-clock"?

For a consecutive clock, should we say point A is before-clock or after-clock?

1 2
__ __
...__| |__| |__...
A

For cycle 1, point A is after-clock, but for cycle 2, it is before-clock.

If it is said the start phase of clock signal is the key, how could designer make sure that the start phase of real application can meet his assumption exactly, no matter it is from pll or external crystal oscillator?

2. For these two protocols, the instruction steps are different. What cause such differences? Why does the reason cause these two different instruction sequence but not others?

3. ATPG default chooses before-clock protocol. If semiconductor vendor specifies other strobe timing information, designer still could use ATPG to generate patterns, but need use the user's test protocol to guide ATPG, right?

Thanks a lot!

qjlsy,

To understand this, you will need to know how ATE (Automatic Test Equipment) works. The tester are usually cycle based, so each test cycle is typically one clock pulse (some advanced testers can do more than one pulse, but let's skip that for now). With one pulse per test cycle, you define the period of the test cycle, when the rising and falling edges of the pulse occur, and when you want to strobe the outputs, all with respect to a single test cycle. So for example, if your test cycle is 100ns (10MHz), and you specify a rise and fall time of 25ns and 75ns, then strobing before 25ns and strobing after 75ns will be 'strobing-before-clock' and 'strobing-after-clock', respectively.
ATPG normally formats patterns with 'strobing-before-clock'. I usually don't use 'strobing-after-clock', so I am not sure what special instruction sequences are needed.

 

[qjlsy]

strobe before clock strobe after clock dft

dr_dft, I got the 1st question's answer from you reply. Thanks a lot, first.

Then about my 3rd question, I don't understand why strobe-after-clock protocol consist of following steps?

data scan in -> parallel measure cycle -> parallel capture cycle-> measure 1st scan out -> data scan out

1. Why need parallel measure cycle be separated from parallel capture cycle?

2. What is the difference of "parallel measure cycle" and "measure 1st scan out"?

3. Why is there a "parallel" measure/capture cycle? In scan chain, all are serial. And in one cycle, only one pin just have one bit output.

Could you give me more help? Thanks a lot!

 

[dr_dft]

creating synopsys test protocol

qjlsy,

Strobing output of scan shifting will only cover faults in the logic BEFORE the scan flip-flop. There are always logic or connections from the last bank of flip-flops to the chip primary outputs that need to be tested. This piece of logic is tested by shifting in a scan pattern into the last bank of flip-flops and then strobing the primary output, which is you parallel capture cycle.

Regarding the measure 1st scan out, since right after the capture cycle, the value captured in the last flip-flop in the scan chain (which is the first bit to shift out) is already at the scan output pin, you should strobe it before the first shift pulse. For 'strobing-before-clock', strobing can happen in the same test cycle as the shift pulse. However, for 'strobing-after-clock', the strobing has to happen in the previous test cycle (before the shift pulse), otherwise we will miss strobing the 1st bit.

Hope this is clear enough.