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hi,
The process you used has chemical mechanical polishing? if no, the surface of upper metal layers will not be flat especially on the top of the double poly cap. It will cause over etching of metal wires over the edging of the poly cap and would cut it.
dracula lvs
Hi all,
Do anyone know how to fix the following discrepancy in Dracula LVS? In my case, I input .cdl netlist for schematics and .gds for layout into Dracula LVS
************** DISCREPANCY 1***********************************
------------------------------------------------MATCHED...
Re: Encounter log file
For the auto place & route, you can follow the steps in the below link:
**broken link removed**
There are some errors of your config files(.conf). You can set them in the GUI of Encounter, so you no need to import your config file.
Only 4 files you need to import to...
Re: Encounter error
what is the error shown when you import this .lef file into the encounter ?
The Encounter will not get physical information from techfile.cds.
Can you attach the .lef file and the corresponding errors shown?
Re: Encounter error
you try only import the following files into Encounter to see whether it is ok or not:
1. synthesized verilog netlist (.v)
2. timing library file (.tlf)
3. library exchange file (.lef)
.lef file tell Encounter physical dimension of the standard cell library. Be sure to...
lvs + verilog
Hi,
How to import synthesized verilog netist into Dracula, so that I can do the LVS between this netist and the resulted auto P&R layout in gds.
Thanks
Re: Xilinx Help
Thanks for your reply.
I found that the "Done" signal didnt go high when starting up. How to fix it ? is the Xilinx chip broken? I can get id code from it and download bitstream data to it.
Thanks :)
I use the Digilab 2E. The Xilinx download program told me it was sucessfully program and verify the Xilinx (XC2E200) by JTAG, but there is no any outputs from the xilinx pins for any input signals ( the location of input and output pins are checked correct) What is the problem of it ? does...
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