Import Synthesized Verilog Netlist into Dracula for LVS

[pyth2004]

lvs + verilog

Hi,

How to import synthesized verilog netist into Dracula, so that I can do the LVS between this netist and the resulted auto P&R layout in gds.


Thanks

 

[pyth2004]

verilog import

Do anyone have some experience of doing this? or exist some other methods for post -layout verification for digital design. Thanks

 

[joefong]

synthesized verilog

u might be able to do that by using "v2lvs" (verilog-to-LVS) tool from mentor graphic. i'm not sure about cadence tool.

 

[shankarmit]

convert the netlist to spice and then import it..

Regards
Shankar

 

[jelydonut]

in IC5033 you can import the verilog directly with LOGLVS..
in IC5141 you must convert it to SPICE first then import into LOGLVS. In this version verilog is no longer supported.

jelydonut

 

[david_zheng]

You can convert verilog netlist by following tools:

v2lvs (provided by Mentor Graphics)
nettran (provided by Synopsys)

by entrying"v2lvs" or "nettran" in your working directory to know which tool is avaliable in your design environment and command option usage in details.

 

[newcpu]

Why not use calibre for LVS? It is faster than dracula.