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Recent content by protonixs

  1. protonixs

    analog layout design

    Thumb of rule when it comes to shielding: Connect the shield where the line is reference to. Example: If the line you want to shield is VP with respect to VSS, connect the shield to VSS. If the the line you want to shield is VCOMP with respect to AVSS, connect the shield to AVSS, and so on. One...
  2. protonixs

    How to design a P+/Nwell Diode?

    The WIDTH and LENGTH refers to the dimension of your PDIFF over the NWELL.
  3. protonixs

    Cadence Graphical PCell

    isn't it that the default value is micron?
  4. protonixs

    current mirror matching

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  5. protonixs

    current mirror lenght

    transistor length should be the same to achieve proper matching.
  6. protonixs

    how cellphone cellphone battery works

    how cellphone battery works How does cellphone battery works? Connecting the ac adaptor/charger without the battery will not power the handphone. Does it mean that the charge goes through the battery first then to the handphone's system? If so, this means that using the handphone while charging...
  7. protonixs

    Resistor layout matching

    where did you get this idea?[COLOR="Silver"]
  8. protonixs

    layout of cascode transistor

    use common centroid... see attached file (from maloberti).
  9. protonixs

    Dummy resistor to be ignored in Calibre LVS run

    how about removing the layer that determines the value of the resistor? for example, if the resistor is diffusion type, just put the diffusion and no other else.
  10. protonixs

    Dummy resistor to be ignored in Calibre LVS run

    there must be a layer that is used to indicate that those resistors are dummy. ask you CAD engineer about it.
  11. protonixs

    Pls check if latchup issue exists in this layout (Taped out)

    Re: Pls check if latchup issue exists in this layout (Taped hello bellona, first of all, the 2 transistors should be laid-out in a common-centroid manner. please refer to the attached figure. should there be any more problem after that, please let us know. regards, protonixs
  12. protonixs

    Nmos substrate connection

    that is the only solution. violating this rule might trigger latch-up because of the potential difference between the 20um region, and beyond it.

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