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I have implemented an asynchronous FIFO
However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.
Both read_clk and write_clk are having the same clock frequency.
Could anyone advise ?
Why some of the corners does not require -data option ?
For library corner TC, why data path does not need -late option ?
For library corner WC, RC corner CMIN, why there is -clock -late option ?
For this vcd file, why is the DRAM read operation (709746ns) not reading back the DQ values written at the same address (4096) during DRAM write operation (709578ns) ?
Note: read and write latency = five ck cycles
what is the purpose of preclock described in https://spdocs.synopsys.com/dow_retrieve/qsc-s/dg/tmax_olh/S-2021.06-SP3/tmax_olh/Default.htm#tmax_cmds/tmax_cmds/man_set_contention.htm ?
when to use postclock or nopreclock ?
For https://www.design-reuse.com/articles/37956/lockup-elements-the-timing-perspective.html , could anyone explain the following timing difference between launch and capture domains ?
With the help from Jeff Bush , the full logic is now simplified with one tradeoff.
The mentioned side-effect / tradeoff of under-utilizing one FIFO entry is also illustrated in the following coverage waveform.
Additional Notes:
1. should cross all bits of read_ptr_gray for full logic generation, and no CDC issues since read_ptr_gray is already gray-coded.
2. Remove read_en_sync to avoid CDC error associated with 'full' logic, but still able to solve the STA issue by choosing not to increase...
Someone told me that I should only cross one changing bit of read_ptr_gray
Any idea how would I do this elegantly without introducing extra STA issues ?
I mean I need to identify which exact bit is the changing bit
Besides, I was also told that using both read_ptr_sync and read_en_sync to...
Increasing the FIFO NUM_ENTRIES seems to have temporarily solved the issue, but I am still searching for a more permanent solution without the need of increasing NUM_ENTRIES
Now, I am facing STA setup timing issue and I did some modification which is supposed to help with setup timing, but...
I suspect that my full logic is still incorrect.
The attached testbench and waveform files are generated from https://symbiyosys.readthedocs.io/en/latest/index.html , and it had not yet triggered the phenomenon where the afifo verilog code failed in Modelsim as you have seen earlier.
looking at your Full_t signal reminds me that you might had overlooked on the effect of gray code on the full check pointers comparison. (check Figure 5)
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