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Hi folks,
I have a basic question regarding PLL clock drivers for DDR applications.
Why is it that PLLs are used when a DLL can accomplish the same function.
Since we are not multilpying the input frequency and we are just buffering the input clock to many output channels, I think that a DLL...
Hi cheneyliu99, please know that psub2/msub is just a dummy layer used to clear LVS. Since it is not a physical layer, the ASUBGND and PWR_SUBGND are effectively shorted.
In case you do need isolation between the two, you need to use deep n-well layer.
If you are using ASUBGND for mixed-signal...
A small addition to what cop02ia already explained.
w in this case refers to the width per finger = 10u
"simM" -- refers to the no. of multipliers.
So, "total" = no.of. fingers X no. of multipliers = 4 X 2 = 8
So, the total width W (and not length "L") will be 10u X 8 = 80u
With fingers, you...
If you are running your simulations on a multi processor server, you can also use the multi threading option. In the ADE window, in Simulation->Options->Analog, you will find a multi-thread option.
You can turn it "ON" and specify the number of threads..the no.of threads will be the number of...
indcutor LVS problem
do go through the PDK documentation...Inductors are special devices and there might be some guidelines for inductor layouts in the PDK doc...You may just get a critical point about inductors in the doc.
Hi,
I am designing a PLL and I'd greatly appreciate it if anybody can answer my following queries:
1. I want to do a stability analysis using phase domain model..So, can I use the model in the pllLib given by cadence? If not, can anybody please give me the phase domain models which I can use OR...
Re: estimate the layout area
You can use the Layout XL tool for area estimation.
In your schematic window, you can go to Tools->Design Synthesis->Layout XL. It will open a layout editor window. From there, you can go to Design->Generate from source. In this form, on the bottom left, you'll...
Hi,
You can check the following link for some tips:
http://www.geocities.com/fudinggecircuit/analogjobguide/Analogjob.html
btw, as dick_freebird already mentioned, the interview questions depend on the type of layouts the opening is for and the experience they are looking for. In general for...
Regarding PLL design
Hi,
I am designing a PLL and I'd greatly appreciate it if anybody can answer my following queries:
1. I want to do a stability analysis using phase domain model..So, can I use the model in the pllLib given by cadence? If not, can anybody please give me the phase domain...
Hi gafsos,
By "high performance", I just meant high gain, supply noise isolation etc. which I mentioned in my post.
Didnt mean to offend digital design here :)
assura hierarchy
Hi Prathat,
I'm not too sure if I'm able to understand why there is a bulk potential problem for the DAC digital part. Is the pwell of these nmos devices(in the dnw) connected to the right potential and does it match with the potential you have connected in the schematic?
Does...
The minimum channel length is defined by the foundry for a particular technology process.
More often than not, minimum channel lengths are used for digital blocks only, since they are the high speed switching blocks and also because they occupy, as a rule of thumb, around 60-70% of a die area...
Re: Help： the difference between via and contact
Adding to Chikva's point, a contact is used to connect POLY or P+/N+ DIFFUSION to the lowest level metal.
Vias are interconnects between successive metal layers.
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