cheneyliu99
Newbie level 3
lvs substrate
Hi All,
I am designing a mixed-signal chip. In my schematic, I used different pins for different signal's bulks. e.g. ASUBGND for analog bulk, PWR_SUBGND for Power circuit bulk, etc. When I do Calibre LVS, whenever I have types of signals, LVS will not let me pass. The reason is that, physically, all these pins share save p-substrate layer.
Is there any way that I can pass the LVS without too much modification. e.g. adding some rule file for LVS saying that ASUBGND equals to PWR_SUBGND etc.?
Or do I have to modify the schematic?
Thanks!
Hi All,
I am designing a mixed-signal chip. In my schematic, I used different pins for different signal's bulks. e.g. ASUBGND for analog bulk, PWR_SUBGND for Power circuit bulk, etc. When I do Calibre LVS, whenever I have types of signals, LVS will not let me pass. The reason is that, physically, all these pins share save p-substrate layer.
Is there any way that I can pass the LVS without too much modification. e.g. adding some rule file for LVS saying that ASUBGND equals to PWR_SUBGND etc.?
Or do I have to modify the schematic?
Thanks!