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Hi,
Are there any knowing how to run mixed mode co-sim on ncverilog?
The command I'm using for the ncverilog is as below.
ncverilog -f ./design.vc -l ./log/design_top.log \
+loadpli1=./nc_loadpli1/debpli.so:debpli_boot \
+pulse_r/0 +pulse_e/0 +transport_path_delays \
+ncstatus \
+access+rw...
Hi,
I'm running a mixed mode design that is using verilog for digital and spice netlist for analog.
The tool is using ncverilog. I'm wondering that I can't see any response from the analog
design on the waveform that is in a fsdb file. Is is a problem on fsdb dump? Suppose,
the dump...
Dear Sir,
I'm running a co-sim by using hsim & ncverilog. Analog circuit is written in spice netlist.
And digital circuit is in verilog. After running, some error message found as below.
Error: parameter "pwr" not found for instance...
Hi,
Are there anyone able to briefly explain this command, report_clock_timing? And, how to explain the content of the report?
For example,
Maximum setup launch latency
Minimum setup capture latency
Maximum hold launch latency
Minimum hold launch latency
Maximum active transition
Minimum...
KCK,
Thanks.
Peter
- - - Updated - - -
If my design is a core limit, to improve the core utilization, needs to reduce the core size?
Or, we can try to do some more efforts on the floorplan and routing?
Peter
- - - Updated - - -
Suppose, for pad limited or bump limited, the utilization is...
Yes. The IOPATH DELAY is
(IOPATH A Y (0.487::0.487) (0.466::0.466))
But the value I saw is 0.213 ns and 0.167ns on simulator.
I used ncverilog to generate FSDB and verdi to check
the waveform.
Peter
Can we keep the design size and increase the utilization by just
doing some more efforts on the floorplan or routing?
Peter
- - - Updated - - -
core utiliztion is a factor decides the floorplan or
floorplan is able to improve the utilization?
I think both floorplan and routing are able to...
Dear Sir,
I met one strange thing that the cell delay value is different from the delay value in SDF file, while doing a post simulation. From the log file, the sdf file has been read. And only
have some unimportant warnings. Why is the cell delay value in SDF different from what
I see on...
Hi,
A little strange for the input of the FF. It should have input connection. Otherwise,
the format of the generated clock won't be known. From your constraints, suppose,
you need a 1/2 clock. It then similar to a circuit in the attached file, I think.
Peter
Hi,
Recently, I have a 0.13um process design which has a core utilization 55.7 %
at pre-CTS stage. The chip size is 1800um x 1750 um. The core utilization
seems not so well. Is it possible to improve? After CTS, will it be changed?
Suppose, clock tree was grown at first, wasn't it...
Hi,
First of all, we should check the report content, by using a command, 'report_analysis_coverage -verbose'.
Then, checking, item by item, I think.
Peter
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