Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: PROCESS
OK, as you new example. Clk and Rst is in sensitivity list, so this process will be execute at edge of Clk or Rst. At the edge only means that different time is -> 0.
I think you may not understand because you always use "signal" type? If you want to learn about sequential of...
Re: input clock problem
you should be check surely that pin 77 is global clock.
If yes, you may not need to set any constraint. It will automatic place gclk by ISE. But please remember, you must not use clock signal as combination circuit.
Re: PROCESS
As your example is not have sensitivity list signal. So this process will always run.
In process, statement will calculate and update signal value at the end of process. So if first condition is not have any effect to second condition, your example seem to be parallel. The opposite...
1. In VHDL level for simulation, You can write VHDL for compare input as 'Z'.
2. Hi-Z is not mean for synthesis. 'Z' is for assign to bidirectional pin.
3. For hardware FPGA is not design to sense Hi-Z state. So you cannot implement to FPGA.
ise create my own ip core from my vhdl code
Can somebody please help me ?
I have my own ip core and I want to distribute it, but I don't want to distribute the source files. I want to distribute it as black box. Example .NGC, .EDIF, ... Somebody know how ?
Because I try to use Xilinx ISE 6.3i...
Re: How is this calculated?
The above is correct calculation. But please take care about real system implementation. If you implement on 32-bit system, and do you want high performance ? Because 32-bit system can work with 32-bit data for read/write. 3-byte (24-bit) operation may difficult and...
Re: VHDL
The tools of VHDL or VerilogHDL is not free, but evaluation !!
You can try to simulator is ModelSim at www.model.com
About FPGA device and tools, you can see the information at www.xilinx.com or www.altera.com.
Re: VHDL
VHDL is a kind of "hardware description language".
Another language is also popular is VerilogHDL.
VHDL style look like a Pascal and also VerilogHDL look like a C.
VHDL is used to designed hardware. And you can synthesis, place and route to FPGA or ASIC.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
