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Hello friends
Any one can clarify my doubt ?
i didn't understand the exact difference between glitch and noise
because for doing si analysis by using cadence celtic,we can do glitch analysis and noise analysis seperate seperately by using different flows and we can do both analysis at a time ...
Hi
if you are working in industry ,you can use updated version of cadence encounter user guide,otherwise you can follow already posted encounter user guide .But the continution of present version in market was 4.1,5.2,6.1.
and you can use cadence source link for forther doubts
Regards
Siva...
Hi to All
I know digital standard cell layouts........
I am new to analog layouts ,so
Can any one explain flow of analog layout from schematic ?What are the constraints we should take to draw analog layouts ?
What is Salicide resister ?what is the difference between salicide and unsalicide...
Hi
I faced this problem in one the interview.what he asked is .......according to my functionality my p-mos and n-mos widths should maintain
equal(not minimum widths)then how can u equalise the rise and fall times with out changing of W and L values ?
Thanks
Sivakumar
Hi
Actually what your explaind is correct but what i am asking is ....
my p-mos and n-mos widths of inverter is same that is .36u for 0.25u technology
p-mos width is 0.36u
n-mos width is 0.36u (these are minimum diff widths for 0.25utech)
we cannot decrease widths below these width because of...
Hi
Both n-mos and p-mos widths are minimum widths(that means we cannot folde it to decrease the rise time ) then
To maintain the equal rise time and fall time to the inverter What are the steps your going to tack ?
Thanks
Sivakumar
metal density error
Hi
generally After routing we are checking metal density errors in Soc Encounter .
Can any one explain What is metal density error why we are going to elimenate metal density errors by adding aditional metal at particular place ?
Thanks
Sivakumar
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