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Recent content by omsi

  1. O

    contacts/Via sizes - any fabrication restriction?

    contacts/Via sizes Why the contact/via sizes are fixed? Is there any fabrication restriction on this?
  2. O

    Why the maximum limit for the diffusion density will be present?

    Why the maximum limit for the diffusion density will be present? What is the reason for fixing those violations?
  3. O

    CDU? Critical Dimension Uniformity

    critical dimension uniformity Hi, Can anyone tell me what is CDU? Why we should have in CHIP LEVEL LAYOUT? I have found this in TSMC 90nm document. Please breif me with any document. Regards, Krishna Kumar Movva.
  4. O

    Why we put a Boron implant / Salicide blockage layer on ESD structures?

    Hello, Can anyone give me the reason why we put an Boron implant / Salicide blockage layer on ESD structures. Also why do we maintain more spacing between diffusion contacts and Active poly? Please Reply ASAP. Thanks in Anticipation, OMSI
  5. O

    Deep Nwell & Shielding

    Hi, Can anybody give a document on Deep nwell process & shielding techniques. Thanks in Advance, Krishna Kumar Movva
  6. O

    Question about RC extraction

    Hey how to give temperature specific extraction using calibre
  7. O

    Nwell different potential spacings

    Hi Sridhar, Yeah i am working in analog mixed signal layout domain.
  8. O

    Nwell different potential spacings

    Thanks Sridhar, Yes, I do agree with your explanation. Its one of the reasons. I read that we can prevent latch doing so. But i dont how actally it prevents. Could you see clarify me.
  9. O

    Nwell different potential spacings

    Hai Every body, Why Nwell spacings for two different potentials is more than n well spacing with same potential? Please clarify me. Thanks, Omsi.
  10. O

    N-type and P-type antenna diodes roles

    well antenna Thanks for your earliest reply. How can we know that the charge formed on metal is positive or negative? if we place N-diode, then it will discharge negative charge and vice versa for p-diode. Now which diode we keep at gate input.And also please tell me the prominance of Tie down...
  11. O

    N-type and P-type antenna diodes roles

    Hello all, I have one clarification, can anyone help me in this? Actually for antenna effects, we keep antenna diode to protect gate from charge formed on long metals connected to gate. Normally which type of diodes are preferable? N-type or P-type? else we should keep both N-type and p-type...
  12. O

    Regarding 65nm DFM Rules.

    Hello, I am working on UMC65nm process.I am getting the DFM error as following: POLY1 gates with width <=0.08um not over TG should be align one direction. Horizontal direction is preferred. Can Anyone tell why those gate orientations are asked to follow in horizontal? Is there any fabricating...
  13. O

    About P+ rppoly and N+ rnpoly...Plz reply

    Nwell is used to differentiate the substrate from resistor formation region. If no Nwell ,active region forms on the substrate and acts as transistor.
  14. O

    About P+ rppoly and N+ rnpoly...Plz reply

    implant layer Thanks Srieda, Why we need implantation for poly resistor?
  15. O

    About P+ rppoly and N+ rnpoly...Plz reply

    p+ implant + poly + resistance Hi , I have a doubt regarding the formation of rppoly and rnpoly resistors. For instance,the rppoly is formed with nwell,p impant and the poly.Here is my doubt. Since we need only poly resistance why we put that poly in P or N implants? why cant we form that poly...
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