Nwell different potential spacings

[omsi]

Hai Every body,

Why Nwell spacings for two different potentials is more than n well spacing with same potential?
Please clarify me.

Thanks,
Omsi.

 

[sridhar540]

Hi


This is sridhar.Your question is really great.


This is because generally the pmos transistors belonging to the same nwell potential are shared.
Even though if they are not shared we need to maintain a vey minimum spacing between the wells belonging to the same potential becuase during fabrication this nwell will extend beyond thier regions
depending on the doping profile so two nwells belonging to the same potential if they are extended they would be joined and no problem arises because they are of the same potential and the concept over here is the sharing of nwells.
But in the case of differentail potentail nwells if they gets joined the transistor wonot work so always we maintain larger spacing for the nwells belonging to the differential potential than the nwells belonging tothe same potential.
Ok byee byeeeeee
send me a reply back about my answer

 

[omsi]

Thanks Sridhar,

Yes, I do agree with your explanation. Its one of the reasons.

I read that we can prevent latch doing so. But i dont how actally it prevents.

Could you see clarify me.

 

[steadymind]

It is mainly done to prevent latch up and also based on the process rules for the technology being used.

when the two n well with different potential overlap or come in contact the they can cause unneccesary body effects. and can lead to formation of two back to back connected transitors which can lead to positive feedback and wreck havok.

 

[sridhar540]

Hi omsi

I am not getting any idea right now but the issue of latchup arises only whwnthe pmos and nmos transistors are present so that a back to back connected bjts are formed and both the vss and vdd are shorted.But still I will ask about this to an expert layout engg from our side and I will try to soon give a reply to you.
I would like to ask what that u are doing.that is ur proffesion, whether are u a layout engg.

 

[omsi]

Hi Sridhar,
Yeah i am working in analog mixed signal layout domain.