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Recent content by obovolo

  1. O

    clock jitter in LVDS transmitters

    +oversampling +cdr +jitter +tolerance if ur signal is not so fast, phase picking oversampling CDR might be a good alternative.
  2. O

    Effects of bond wire on LDO design

    Bond Wire the bondwire might start effecting ur circuits around 100Mhz if ur caps of the LDO are not so small. Be aware of ur PSRR > 100Mhz if u want to use the LDO as a power supply of analog circuits.
  3. O

    Need help about receiver noise figure measurement

    get a NF measure scope first
  4. O

    CMOS down conversion mixer

    i think u better take some course at school or ask ur teacher, TA and ur simulation tool
  5. O

    Problems with a PLL: Transistor Sizing (VCO related)

    PLL: Transistor Sizing ? for each delay cell in ur vco, there should be a buffer with it. say A is ur delay cell, B is the buffer, ur vco should be like A1 drives A2 and B1, A2 drives A3 and B2, and so on. and make sure each delay cell has the same loading.
  6. O

    Problem with PLL constructed with VCO

    PLL Construction what is ur ref freq? maybe ur Kvco is too large
  7. O

    How to estimate the junction cap between the seperated pwell and the nwell?

    Hi, I'm designing some high speed stuff and somehow deep nwell is required. but i have no idea about how to estimate the junction cap between the seperated pwell and the nwell. (for an nmos source follower, the junction cap will introduce addtional paracitic) cuz i'm using tsmc mixed-mode...
  8. O

    designing pll for 100MHZ

    vco pll 100mhz try some basic/advance analog/PLL design books about the open loop and close loop stuff, and u'll get the idea
  9. O

    What are the salaries in Asia?

    Re: Salaries in ASIA USD, some ppl r really paid equal or more than 100kUSD/yr in taiwan
  10. O

    What are the salaries in Asia?

    Salaries in ASIA some ppl in taiwan can get more than 100k/yr as just new grad master
  11. O

    Doubts about PLL and oscillator in RF transceiver

    PLL&Oscillator if u can make sure ur osc work correctly, u don need pll, just like xtal osc. but most VCO's freq always vary significantly with temp and process variation. if u use ur scope to c ur osc freq, u can easily see that ur freq is moving.
  12. O

    i like to switch to vlsi

    get some books take some courses
  13. O

    What are the required GRE and TOEFL scores for studying in the US?

    Ideal Gre scores u don need to get amazing score but it still hard to get a design job
  14. O

    What is the future for CMOS Analog IC Designers ?

    so how to become a boss?
  15. O

    How is VLSI Jobs in US now

    vlsi jobs for freshers in china it is possible but not easy
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