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Recent content by noura7

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    multirate FIR filtering process

    Hi, I have a simulink model design of three cascade interpolator FIR filtering with samples times respectively 128 kHz, 512 kHz and 8.192 MHz generated by a Digital PLL that clocked the filtering process. Please can any one help me how can i connect the filtering process with digital PLL in...
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    Counter FPGA implementation

    Hi all; Can any one please tell me why can not find the implementation for block Counter of Frequency Divider1 ??? and what can i do ??? thanks a lot Noura
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    Modelsim PE Student Edition 10.1c

    Hi all, i have downloaded the latest version of Modelsim PE Student Edition 10.1c. Why this version does'nt support hdl cosimulation simulink/Modelsim??? thanks, Noura
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    how to write a matlab code 24 bit fixed point sine wave

    hi all, Please can any one tell me how can write this matlab instruction "u = 0.5*sin(2*pi*ftest)" for a sine wave in 24 bit fixed point representation? thanks a lot, Noura
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    HDL coded digital to bcd (binary-coded-decimal) conversion

    Hi all, In the process of digital to analog conversion, the thermometer code output, corresponding to the digital value of the input signal, activates the unit value of the analog entities (which may be current or voltage sources). The analog output is the summation of all those activated...
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    how can resolve Delay problem with hdl code of interpolation FIR filter?

    the filter length and sampling rate were about respectively 325 and 8 MHz.
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    how can resolve Delay problem with hdl code of interpolation FIR filter?

    no, it is a simple cascaded FIR structure
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    how can resolve Delay problem with hdl code of interpolation FIR filter?

    Hi all, I have an interpolation FIR filter that i have simulatated with matlab simulink environement, there is delay when data is upsampled but this delay is becoming much when i describe this filter with vhdl code. How can i eleminate the delay difference between simulink and ModelSim? Thanks...
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    3rd order digital sigma delta modulator

    Hi, Please can any one tell me why the amplitude level of an input signal of a 3rd order sigma delta modulator block attenuates when i make comparaison between Matlab simulink and modelsim results and i don't introduce any non-idealities. thanks in advance
  10. N

    ADPLL versus analog PLL

    hi, can any one please give me why the all digital pll (ADPLL) is most used in digital system that can be then implanted with FPGA technology than aclassical PLL (anlog PLL) thanks
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    Synchronize multiple sine wave oscillators

    hi, can any one please give me why the all digital pll (ADPLL) is most used in digital system that can be then implanted with FPGA technology than aclassical PLL (anlog PLL) thanks
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    dynamic element matching technique

    hi, Can any one one please give me the difference between R2DWA (second order Data Weighted avereging) and BIDWA (bidirectionnal data weighted avereging) techniques. thanks
  13. N

    HDL Cosimulation blocks in Simulink

    no i can describe one component with vhdl or verilog language but one i have for example 4 components how can i instantiate and connected them together. Can you please give an file example to follow that thanks!
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    HDL Cosimulation blocks in Simulink

    please can you give me an example (.v or.vhd) file
  15. N

    HDL Cosimulation blocks in Simulink

    sorry for that. I know HDL file that's mean VHDL or VERILG file. For the first time i hear about the word "wrapper" that's make confusion for me
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