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"there is no need to connect all IP's signal IOs to AMBA bus,is that right?"
it is right..
"for AHB,could you tell me the typical bus clock frequency"
for 0.18 process typically, goal for 100 -200Mhz can be achieved. but more is hard. if many devices is connected in the bus.
generally, Bus is a...
if you have a ip that has had a AMBA interface, you should ensure your interface meet some timing constrians. otherwise you will meet the timing closure problem in P&R. in our lab, every Io of interface to AMBA has constrain about at least 50% duty time both for inputs delay and outputs delay...
short violations in soc encounter
now, Soce have a doc with the timing closure. and it gives some good comments about how to do floor-plane and pw-plane when considering the timing closure. you can read it. it may be helpful.
cts file for encounter
SDC from front-end sythesis tools can be used to constrain the Clock tree. it also the front-end designer want the clock tree should be.
really??? In our lab the top metal is used to route gobal and critical net and only the second and third level from top is used to power. any comments???
latch time borrowing
yes. if you are interesting in this you can read this book more detail.
something about this :
---------------------------------------------
Slack passing is possible with level-sensitive latches or cycle stealing, by
careful scheduling of the arrival of the clock edges at...
i agree with this. my suggests is using phycial synthsis to synthsis the design in DSM era, like PKS and PhyCompile, all of those have commands to fixed setup and hold with some knownleges of layout or placement, can short your iteration of timing closure.
Re: emacs for ASIC
Yes. these modes are not only the key word highlight but also some powerful functions. for example in verilog modes some functions like /*AUTOINST*/ /*AUTOSENSE*/ and so on can improve your productives.
and with the help of shell commands you can copy and modify some logs...
Re: PCI pad Vs. CMOS pad
radix may be right. you can find those in PCI standrant. if you want learn the detail your can reference the pad's circuit schematic which is often come with the PAD lib. in my mind TSMC and SMC contain it.
I am agree with you about the asynchronous circuit will play a great role in the future's digital design. but i think that the synchronous circuit will still the most important methods in future even thought more powerful synthesis eda tools can be used for asynchronous circuits . because man...
for ADC, if you means your synthesis is tranlate behavior RTL to netlist. i am afraid you can't. your lib may be only the GDSII lib or some abstract model. those don't not include the enough info to DC . but you can instance those modules in your design then link them in DC if you have the...
here is some advises. maybe useful to you :P
1.you can try config your xserver with a normal SVGA card. maybe it will work.
2. if you want to install the EDA software. you had better have the swap space upon > 2*GB, many EDA eda software need it urgently . especially the synthesis and P&R...
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