Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by nisshith

  1. N

    Clocks in SDC and corresponding creation of similar clocks at no particular pin

    there are no drawbacks in defining virtual clocks its a requirement you have to do it. If you don't your path remains unconstrained and you would not be able to analyze I/O paths. whenever there is a path between a flip flop sitting outside the chip and a flip flop sitting inside the pin, we...
  2. N

    Clocks in SDC and corresponding creation of similar clocks at no particular pin

    Firstly, It may happen that the Virtual clock (Clocks capturing or launching data to IO ports) does not have same frequency as the system clock. Also the points launching or capturing these data are not actually on the chip therefore we cannot define the end points in clock tree.
  3. N

    Clocks in SDC and corresponding creation of similar clocks at no particular pin

    virtual clocks are clocks which are essentially to models the clocks outside chip. They are used while analysis of Input-> reg or reg->output paths.
  4. N

    what do you mean by retaining_rise & retain_rise_slew

    retain arc is basically Clock-> Q arc in D Flip Flop. Retain time is defined as the shortest delay from input port (CLK) to O/P port (Q). therefore the definition on retain_rise_slew and retain_rise is apparent.
  5. N

    Pattern matching using state machine

    it will work fine in verilog but i think it will take more hardware, not a feasible design.
  6. N

    Pattern matching using state machine

    first mistake is that if it is a sequence detector input must b of one bit only with one bit coming in on in every clock cycle. u have to make a state machine first. i think it will have 12 stages hence 4 flip flops must be used to control state vectors. Make a state machine and do the verilog...
  7. N

    [Layout] What is LVS and why is it needed?

    Layout Vs Schematic (LVS) is used to check connectivity in the final GDSII. Final GDS is compared with the netlist to check whether there is a mismatch. Otherwise it can lead to a circuit failure.
  8. N

    How a cell delay characterization is related to endcaps/fillers

    at end of every std. cell row we need to tie N-well with VSS and PWell with Vdd. for this purpose end cap cells are used.
  9. N

    Question for Frequency divide by 3 of 33% and 50% duty cycle

    much simpler code for Divide by 3 clock with 33% of duty cycle Try this one. module div3_a(clk,clk_out); input clk; output clk_out; reg reg_a, reg_b; wire regb_in; initial begin reg_b= 1'b1; end assign clk_out = reg_b ; assign regb_in = ~(reg_b|reg_a); always @(posedge clk) begin...
  10. N

    difference between multipoint cts and distributed clock network

    MPCTS can end up having larger skew, insertion delay would be less. No. of clock buffers and inverters added will be almost same (can be less also)
  11. N

    Career Path Physical Design CAD - Methodology & Automation Engineer

    I want to know the career path of Physical Design CAD - Methodology & Automation Engineer, after few years where would I be if i start today with this job profile. can i move to any other domains using experience in this field?
  12. N

    component instantiation query in verilog

    it may be correct in your case. actually comp X(.a({b,a}), .b(c)) will give different results in definition "input [1:0] a" and "input [0:1] a", so whatever comes in RTL go with it. I always get confused in this.
  13. N

    component instantiation query in verilog

    i think comp X(.a({a,b}), .b(c)); will give the desired result. check in the RTL view.
  14. N

    component instantiation query in verilog

    write comp X (.a({a,b}),.b(c));
  15. N

    [SOLVED] Maximum radius of single pickup in well tap cells

    yeah it is called maximum radius but it is a pre-defined value.
See more

Part and Inventory Search

Back
Top