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Recent content by newbie_1

  1. N

    how to remove switch glitch?

    hi, To generate a positive pulse, a switch is used with a pull-down resistor. But glitches would come out when the switch is tapped to connecting to power suppl. Then how can I remove the glitches? thanks a lot
  2. N

    What is the sub pin in dgncap of samsung65lp?

    dgncap hi, In the process of samsung65lp, there is a cap model of dgncap. There is pin named as "sub". Can anyone give me any idea what this pin is and how I should connect it ? thanks newbie
  3. N

    How to calculate wire capacitance?

    cpersqdist hi, How can i calculate metal to ground capacitance using CPERSQDIST defined in LEF file? Suppse CPERSQDIST=1e-5, L=100um, W=0.2um thanks
  4. N

    how to define 2 nets are same in spice netlist?

    *.connect spice netlist thank u for ur reply. But actually i wanna set two nets to be same in netlist such that i can run lvs. Since 1 net is defined as global signal in the netlist , then how can i define another one to be same as that one? thanks
  5. N

    how to define 2 nets are same in spice netlist?

    short in spice netlist say, .global net1 net2 how to set net1 is same as net2 globaly? thanks
  6. N

    The question about ADC-----Is my analyze right?

    and how about those at fs-n*fin? Added after 5 minutes: and make sure fin/fs=cycles/N when doing fft, where cycles and N are natually prime for more random and white quantization noise
  7. N

    Assura RCX scripts for tsmc65lp

    hi, Does anyone has the rcx scripts for 65nm of tsmc? and can you share it with me？ thanks
  8. N

    cdl netlist generation

    aucdl view generation thanks kumard, what do u mean by having the hspice version of the resistors in the cdl? is it due to the properties if the view of auCdl of rppolywo? if so, what can i do?
  9. N

    cdl netlist generation

    cdl netlist hi, two hcells such as rppoly and rppolywo are used in the schematic. During generating cdl netlist of the schematic, rppoly can be generated in to subckt while rppolywo cannot, that is, no ".subckt rppolywo ... .ends" can be generated. what can i do ? thanks
  10. N

    hdmi inter-pair skew testing

    inter pair skew hi, i am on the testing of a hdmi transimitter, since hdmi can output 10 serialized bits then what is the skew between clock and data? it the lsb of the data or any bit of the data? then when i test the inter-pair skew of data pairs, it always stops when serial triggering, and...
  11. N

    how to increase frequency range of DLL?

    hi, i wanna design a DLL with the lock range of 100Mhz to 600Mhz while the power is 1v, how can i make the range so wide since the power supply is only 1v? can anybody give me any help, and share me some papers? thanks
  12. N

    how to design a dll with programmable resolution?

    thanks the input range is about 100Mhz~800Mhz, and the phase resolution has to be programmed from 0~120, can you give me any suggestions or papers? thanks a lot
  13. N

    References about digital DLL and a Verilog model

    hi, can you give me a clarification on dll? and what about phase interpolator, how can i use the interpolator? and good papers will be appreciated. thanks a lot newbie
  14. N

    question about filtering in RCX

    anyway, i cannot find the manual, maxwellequ, can u help find the manual for rcx? thanks a lot
  15. N

    question about filtering in RCX

    hi elbadry, then what about the value to be set in the textbox beside MinC which seems to be some kind of % value? thanks
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