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SRAM macro is generated by memory compiler.
If the highest metal of SRAM is top-2, can we use top or top-1 metal to route across SRAM macro ?
Is there any potential risk ?
My senior colleague in company replied me.
False path is just timing constraint, not effect CTS and won’t be see.
CTS is just balance leaf pins of its create clock.
Each “create_clock” won’t balance to each “create_clock”.
Eg. A clock may 1ns latency.
B clock may 5ns latency.
There are two clock made constraint as create_clock.
If I don't set false_path about these two clock.
After CTS, are these two path balance ?
What action does CTS handle false_path constraint ?
For CTS, these two clocks are treat as independent and have not balance ??
Thanks.
In my RTL design, I insert gate cell (ex: BUF, AND, MUX) for some consideration.
But I don't want to run RTL simulation with cell delay.
How should I do ?
Thank you.
- - - Updated - - -
I know how to run simulation without cell delay.
Just need to apply +nospecify to run simulation.
jpeg encoder verilog source code +download
This website is so strange.
http://www.geocities.com/faisal006/Project/*****
Sometimes it's ok, but sometimes it's not work.
modelsim coverage report
Dear Sir,
Does any body know how to generate code coverage report using batch mode in modelsim or questasim ?
Please teach me.
And how do I explain generated report ?
Thank you very much.
Re: Pure stable clock source
Unstable means that clock frquency changes hugely sometimes.
In my design, there is one stable clock, oscillation clock.
I can use it to detect input clock.
But I don't know what design is good or how to design a good detection circuitry. This detection circuitry...
Pure stable clock source
Hi, I had a problem in my system. The clock source may be unstable. This unstable clock source cause my system to output garbage data. Although my design system can be recovery after clock is stable. But my customer argue this problem. I have to design a robust system...
Re: DDR SDRAM
Your question is so strange.
All operations we can do are listed in DDR SDRAM datasheet.
All support commands are also listed in it.
Of course, you can have if this DDR support this command.
why we need clocks
If we don't use DFF to latch data, we can't know the data process time.
In out application, we always do some math calculation or timing control.
If we don't use timing aspect in our design, it is always problem to real result.
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