Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have started using assertions recently, and there is a relatively common case I can't seem to figure out the correct syntax for. Hopefully, someone in here can help me.
The basic idea can be illustrated by a short example:
property p1;
@(posedge clk)
$rose(sig1) |->
[0:$] $fell(sig2)...
I have been using Icarus Verilog along with gtkwave (on various versions of Ubuntu) for a little while now, and it has been great. However, I have recently stumbled onto a problem I am unable to solve.
This is the makefile I use (simple makefile, that I pretty much found online) :
VERILOGEX =...
Thanks for the reply. Well, the testbench you refer to would be a good test for the whole system. My point however, is that during development of this system, I would want to test the sub-modules (like s_box for example). This makes it easier to explore every module more closely (test its...
Whenever you have a system of some size, there will be several modules. Some of them may be "deeply" interconnected and others more independent. Regardless, you should always verify the modules seperately (not every counter etc. but every major module) before connecting the whole system, in my...
Well, the reason is to keep the testbench readable and maintainable. It contains 20+ interconnected modules, and would therefore become very large, if all modules should be thoroughly tested in one single file.
My intent is to generate the clocks, instanciate modules etc. in one "main"...
I am using Verilog 2001. I have some questions regarding partitioning a testbench into multiple files.
I usually just make a separate testbench for every module, but in this case there are number of modules that all rely on the same clock signals (and each other). Having separate testbenches...
I have actually read that note before. However, phase aligning the clocks is one way of eliminating the need for synchronizers, as far as I have understood.
The risk of metastability is not the issue here, but rather the use of clk_slow in combinational logic (not acting as a clock signal as...
I need a pulse of 1 clk_fast cyle duration, whenver clk_slow has a rising edge, in order to make a time stamp (of sorts) in the clk_fast domain.
Clk_slow and clk_fast are phase-aligned and generated from the same source. Clk_fast may be anything from 2 to 32 times faster than clk_slow.
I have...
OK. So a signal transitioning from '1' to '0' on a given posegde, is guaranteed to be read as a '1' one that specific edge (assuming that the logic seperating the FFs is minimal)?
I always assumed that allowing half a clock cycle for "settling" time was the preferred solution to any modules...
I know that when dealing with an asynchronous signal, synchronizing flip-flops are used to avoid metastability.
As far as I can understand, metastability is caused by the data input changing at approximately the same time
as the clock signal (of the fip-flop), thus vioalting the setup or hold...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
