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Recent content by Mukesh10

  1. M

    USB Response by host during IN transaction when device return corrupt data.

    Hello Folks I have a question regarding USB. In USB 2.0 Host can only return ACK for correct data. Lets suppose we got corrupted data from slave device then what master(Host) will do ?. If slave didn't got any response then what it will do ? Thanks & Regards Mukesh Goyal
  2. M

    [SOLVED] Best tools for using verilog??

    you can use Questasim student Edition, Ncsim , VCS .
  3. M

    Cadence Incisive $shm_probe failed warning

    Hello Everyone i am getting a warning because of $shm_probe failed. ncsim: *W,SHMPFL: $shm_probe failed. Can anyone tell me how to remove that warning. Thanks And Regards Mukesh Goyal
  4. M

    AXI protocol and ARVALID & RVALID

    Hello Sun_ray In AXI our master need to send address only one time(stating address only) . Incrementing the addressing on the basis of control information is the work of slave. we sample address and control information only if your ARVALID is high and in case of response the response is valid...
  5. M

    Questasim Warning vsim 3008

    Thanks dave your reply really helped me a lot !! Thanks And Regards Mukesh Goyal
  6. M

    AXI protocol and ARVALID & RVALID

    Hello ARVALID is in address read channel. When ARVALID is high it mean the the address and control information on the Address read channel is valid. the slave will respond to that address and control information.
  7. M

    Questasim Warning vsim 3008

    Hello Everyone Can anyone tell me wat is the meaning of this warning and help me in removing this warning : Thanks And Regards Mukesh Goyal
  8. M

    [SOLVED] Can i pass mutiple interface to a module ??

    Thanks Dave for your reply the problem is solved. i made a mistake i declared the file name with extension .v thats why i was showing problem.
  9. M

    [SOLVED] Can i pass mutiple interface to a module ??

    Hello Everyone i am trying to pass mutiple interface to a module but it showing some problem. can anyone help me Here is the code : module dut_top#( parameter WB_ADDR_WIDTH = 16, parameter WB_DATA_WIDTH = 32, parameter SOC_BASE_ADDRESS =...
  10. M

    [SOLVED] I2c Arbitration lose

    Hello Everyone. i am working on verification of I2c. i have a question on arbitration in i2c. whenever there is arbitration lose in i2c an interupt is send to cpu. CPu will check the interrupt weather it is for Arbitration lose of data read/write complition. what will CPU do if the interupt is...
  11. M

    [SOLVED] AXI Interconnect Problem

    Hey thanks !! my approach for the arbitration is same. i am checking valid signal only. Actualy someone asked me this question in a interview and i answerd the same as u mentioned but he literally laughed at my answer that arbitation in AXI is based on valid signal generated by master. so that...
  12. M

    [SOLVED] AXI Interconnect Problem

    Hello Everyone I Have developed Multile master and Multiple slave VIP for AHB. and Developed Single Master and Single slave for AXI.now i want to develope Multiple Master and Multiple Slave VIP for AXI. but i dnt know about arbitration in AXI. there i no req signal in AXI as in AHB. any little...
  13. M

    [SOLVED] Multiple instance Intatiation

    Hello Everyone. Can anyone help me in Multiple interface instantiation in the module and how to drive these interfaces. here is the code : // Interface File interface intf_i(input clock); logic[3:0]a ; logic[3:0] b; logic[5:0] c; clocking cb @(posedge clock); input a; input b; output c...
  14. M

    Trasfer of data from register to buffer takes clock cycle or not

    Hello everyone I am working on Advanced Encryption Standard in which i have to transfer data from input 32 bit register to 128bit buffer. whether it takes clock cycle or not ? Thanks Mukesh Goyal
  15. M

    S-Box creation in the Advanced Encrypted Standard(AES)!!!

    @jason its very simple method to implement AES through combination circuit . you have to search on Google for combination circuit or hardware implementation of AES. each operation is implemented separately by combinational circuit like s-box , mixcolumn, shiftrow and all .
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