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Recent content by mujju433

  1. M

    doubt on simple verilog program

    module intra_assign(); reg a, b; always #2 b=0; initial begin a = 1; b = 0; #4 a=0; #6 a=1; end initial $monitor("TIME = %d A = %d B = %d",$time, a , b); initial #20 $finish; endmodule Questions 1. Why for the above code the output is not displayed at 2ns,6ns...
  2. M

    Why Current mirrors with beta helper come into picture?

    Dear friends, I would like to know why current mirrors with beta helper came into picture. I know that current mirrors are the circuits which produces output current which is an the exact replica of Iref or input current or it can be greater or less than the input current, depending upon the...
  3. M

    In Pseudo NMOS how the dynamic power is reduced due to less loading effect ?

    Thanks a lot Praneeth, I understood now.
  4. M

    In Pseudo NMOS how the dynamic power is reduced due to less loading effect ?

    Hi everyone, I would like to know how a dynamic power depends upon the Load capacitance? If this is so then Please let me know how the dynamic power is reduced due to less loading effect in Pseudo NMOS logic. Does Load capacitance depends upon the NMOS transistors? If this is so then it would...
  5. M

    Question on BiCMOS Inverter

    Dear CM Krishna, In the text it says that in condition 1 , Capacitor charges to Vdd-Vbe , i.e assume 5-0.7 =4.3 and then it fully charges when Q2 cuts off, As per your reply , Vdd-Vc<Vbe2 and Q2 is off , How?, What is the value of Vc here? Initially Q2 is ON, What makes it off?
  6. M

    Question on BiCMOS Inverter

    Hi Everyone, Please find the attached document for the BiCMOS Inverter and clear my doubts. I have posted the entire explaination of the same and at the end there are 2 questions. Regards Mujju433
  7. M

    I need a CMOS transistor diagram for Y=A-B and Y=((A+B) whole bar + AC) Whole bar

    Can you please draw for Borrow and Difference together? I hope it become little bigger transistor level circuit.
  8. M

    I need a CMOS transistor diagram for Y=A-B and Y=((A+B) whole bar + AC) Whole bar

    Can anyone help me in drawing the cmos circuit for the below mentioned expressions Y=A-B and Y=((A+B) whole bar + AC) Whole bar
  9. M

    Question about a reg to reg path

    Reg to Reg path i am also getting the same statement wt do u mean by this paths not in the reg to reg paths are added 1000ns so wt do u mean by that Bye take care Added after 2 minutes: iwpia50s tell me one thing if i want to remove the violation for a reg to reg path then wt shd i do? i...
  10. M

    INTRINSIC DELAY ? FAN OUT DELAY ?

    Intrinsic delays means the delays which are due to the internal gates which are there in ur flipflop which may not propagate the data properly Fanout delay means ur driving capability is more than the expected...suppose ur constraint is 20 for each cell and ur cell is driving more than 20 then...
  11. M

    Violations on clock nets after doing preCTS in Wncounter

    PRECTS in encounter its DRV not DRC...DRC is for opens, shorts and antenna violations got it?
  12. M

    Difference between Buffer and clock Buffer

    Hi rajesh can u plz explain that example i did not understand............U mean to say 6 clock buffers is equal to 12 clock inverters right? then wts this statement?? 4 clock buffers and 2 clock inverters effectively you are using 10 npn transistors in the 2nd case as opposed to 12 npn...
  13. M

    Difference between Buffer and clock Buffer

    Clock inverter is also there???????????
  14. M

    which ie better nand or nor latch?why

    I too prefer Nand because nand occupies less space in die If u calculate the logical effort of nand then u will get the value as 4/3 and for Nor it is 5/3 so nand is having lesser delay so thts y we using nand rather than nor and if u consider the rise and fall times of nand and nor also..it...
  15. M

    very important question in SOC encounter take a look at this

    What is shrink factor? I got one answer by analysing When we are generating the cap table for rc extraction for accurate values we need LEF and ICT file and we need to give shrink factor as 1. So what is the need of LEF file bcz LEF contains the same things which are there in ICT file but...
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