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This circuit is a DC voltmeter, I want to know why the two transistors are arranged in this manner?
Is Q1 is common emitter and Q2 is common collector?
why suppely E connected like this?
Do you mean the USB blaster instead of the whole grey cable "between the Kit and my laptop directly"?
This one https://www.amiga-shop.net/en/Amiga-Hardware/Other-hardware/USB-Blaster-Programmer::1121.html ?
I'm trying to program CPLD MAX 7064 and I found it works with Quartus 13. I installed it but I have this problem!
All drivers are installed and JTAG services are running.
I mean that I tried this C <= A AND B; and I burnt it, when testing the code using switches and leds, it acts as OR function.
then I tried this (as a separate code) C <= A OR B; And also burnt it, when testing the code using switches and leds, it acts as AND function.
Is selecting a package...
I'm using Virtex II pro (XC2VP30 and the package is FFG968). I knew that it worked with Xilinx ISE10.1, but I found only the package FF986 (without letter G). The kit is recognised by the ISE10.1 and I burnt simple designs such as AND, OR operations.
I found that AND gives the operation as it...
In digital phase-locked loop, when we change the biased voltage of the system the output frequency increase as the voltage increase, while the power made some fluctuations not logical, at low voltages the power is high and decreases with increasing the voltage and then decreases at high voltages...
I need the function of clock gating in my design (for some circuits that are idle for a while of time to save some of the dynamic power). So, after searching I found that BUFGCE is the best clock-enable circuit for FPGAs.
1635498688
I need the function of clock gating in my design (for some...
I used around 16 BUFGCE in my design as a clock buffer, it passes in the synthesis step, but it gives me this error in "place_design" step:
[Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair. If this sub optimal condition is acceptable for this design, you may use the...
Thanks for all the comments and this useful discussion, but now I'm confused because I'm going to implement this model using VHDL
I will use Xilinx Virtex7 FPGA,
I tried solutions of @andre_teprom and @kaz1 in simulation, they worked well.
I want to make a global solution of clock gating without...
this concept "Clock multiplexer for glitch-free clock" is suitable for two sources of clocks and I want to mux between them isn't it?
in my question, I have only one clock source and I want to time multiplex it for the two functions, ex. I want function_1 only to see the clock when I select that...
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