Power fluctuations in digital PLL

[MSAKARIM]

In digital phase-locked loop, when we change the biased voltage of the system the output frequency increase as the voltage increase, while the power made some fluctuations not logical, at low voltages the power is high and decreases with increasing the voltage and then decreases at high voltages
What is the reason behind this fluctuation.

 

[d123]

Hi,

Do you mean: the higher the frequency, the lower the peak voltage of the output signal?

I could guess that higher frequency = lower gain and lower frequency = higher gain. Or, that the faster the switching speed, the less time the signal has to reach its highest potential and gets stopped somewhere between 0/L and 1/H.

The faster the frequency, the more effect the assorted - at lower frequencies, irrelevant - capacitances will have and cause the above.

Maybe.

Do you mean frequency vs circuit power consumption instead of frequency vs signal amplitude?

One vague guess for that would be that at lower frequencies, switches switch for longer and burn up more power during the transitions and at higher frequencies as transitions from H to L are faster, devices burn power for less time. That theory goes against: higher frequency = greater switching losses due to greater number of H>L and L>H transitions in same amount of time...

A 'scope capture or simulation result of what you describe would help a lot.