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Hi every body
How we can measure the output resistance of any circuit (output terminal) using Hspice code?
I want a code (Hspice) that measure the output resistance of the circuit from output terminal (i.e. CMOS inverter output terminal).
Thanks and waiting
qfn breadboard
Hi,,,
I fabricate a chip and its packaged on QFN, when I conduct my test, I used QFN adapter to insert the QFN chip in it , then insert the adapter on breadboard for testing. I use function generator to generate a square pulse as input to the chip, where I use Oscilloscope to...
inverter overshoot miller effect
Hi ,,,
This overshoot/undershoot is due to the transmission of the input slew to the output throughout the input-to-output coupling capacitance (Auvergne, Daga et al. 2000). That coupling capacitance is affect of Cgd-p,n overlap capacitances at the output, and...
cmos inverter overshoot
Hi ,,,
I design a CMOS inverter using 0.35u process, and I test its output by input different frequency square pulses.
The output of the inverter get distorted after 1M, is that due to RC parasitic introduced by fab. process.
Also, why there is overshoot and undershoot...
Hi ,,,
the circuit which I test is SCL inverter, I designed to be supplied by Vdd=3.3, and the inputs are two square pulses 0-3.3 V opposite to each other (one rise up, second fall down). The power supply is external power supply adjusted to give 3.3V with max. 5mA.
Thankx
HI ,,,
I connect the voltage supply to my circuit and I setted to supply Vdd of Max. 3.3 volt, but when circuit working I found the Vdd rise up to 4 volt (DC Voltage supply).
I don't know why? any help?
( I connect the VDDO=ESD protection to Vdd too)
Thanks
IC TEST ???
Hi ,,,
I got my designed IC on QFN7x7-48 package. Any body has any idea about the testing? what is the type of socket should I use? The max. freq. which use to test is around 5MHz. Can I solder it directly on PCB? but the space between the pins is 0.5mm,so, how!?
Plz, any ideal or...
Hi ,,,
When designing IC , it's suggested to use specific off-chip pin type for each of I/O signal port. Vdda for power, Vssa for ground, Vin for in signal, and Vout for out signal. they also recommend to used Vddo. it's not connected to any port internal the chip. The Vddo pin is connected to...
From Spice to Schematic
Hello ,,,,
I s there any program can draw the ckt schematic from spice netlist format, I mean it's input will be ckt netlist in spice format then its output a schematic of that ckt .
lvs unattached port
Hello every body ,,,
I looking for some info about calibre interactive. I am using cadence virtouso to make some layouts for 0.35um tech and for DRC , LVS and PEX I'am using mentor calibre interactive. Also I use Cadence Virtouso for schematic capture.I could succussfully...
HI,,,
the problem I use Spectre for sim. , but due to unavailability checking facility under Cadence environment we use caliber which output extracted data in Hspice format, so we have to use Hspice for post-layout sim. .
So, how we include extraction data in Hspice netlist file?
thanks
HI,,,
i want to include the extraction data in post sim. by Hspice. How to do that?
I did DRC, LVS, and then the extraction using Caliber. The output extraction file I want to sim. the netlist with it using Hspice , how?
help plz
thanks
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