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Recent content by modelsim62c

  1. M

    How to Select Foundry

    how to select a foundry "How to select a foundry (for standard-cell ASIC)?" To answer this question satisfactorily, you'll need to know a lot of details about your project. On the technical side, does it have mixed-signal (analog) components, like special I/O requirements, PLLs, ADC/DAC...
  2. M

    Companies using platform based design methodology??

    WHA?!?! I answered the WRONG question, but you were kind enough to give me help points :) In general, since the foundries "write the book" on their own fabrication products, you have to request the material directly from them. Most require you to sign an NDA (non-disclosure agreement) with...
  3. M

    Companies using platform based design methodology??

    What do you mean by "platform" methodology? Are you talking about chip-design with standard-cell ASIC? If so, then most companies go with the foundry's recommendation. For example, TSMC has a 'reference design flow' for all its major logic process-nodes (130nm, 90nm, 65nm, etc.) The...
  4. M

    Is system verilog the future??

    'e' is not free, and only one vendor (Cadence) really supports it. What areas is 'E' better? I'm curious, since I know Systemverilog tries to do everything (RTL-constructs, testbench costurcts, assertions, OOP testbench). It doesn't surprise me Systemverilog sacrificed some specialized...
  5. M

    SystemC will die? Why, can anybody give an explain?

    SystemC has the nice property that anyone can download the OSCI materials for free (including the reference-simulator), compile it on a Linux/PC (using gcc), and get some practice. However, like other people pointed out, SystemC has a small niche in the EDA/chip-design industry. It cannot...
  6. M

    Does modelsim support systemverilog simulation now?

    verilog system verilog modelsim forum Mentor offers two different levels of Systemverilog support. For Modelsim PE/LE/SE, the Verilog-license gives you Verilog and Systemverilog(Design) support. Systemverilog(Design) means language constructs for synthesizeable-RTL. To get COMPLETE...
  7. M

    help me with fwrite and fopen commands in Verilog

    Re: fwrite and fopen Which simulator are you using? If you are running a Windows-based Verilog simulator (such as Modelsim/PE), then remember to execute $fclose() at the end of your Verilog program. Otherwise, the operating-system (Windows) won't update/release the open-textfile until you...
  8. M

    which starter kit can i use?

    Not too many 'starter' boards come with GbE (gigabit ethernet.) Off the top of my head, there is the Xilinx Spartan-3A/1800 DSP ($399 USD) and Xilinx Virtex4/FX-12 ML403 ($399 USD). However, the Microblaze softcore CPU isn't fast enough to use GbE -- you can use the GbE link, but it'll run at...
  9. M

    verilog ('include) problem

    In the Xilinx project manager, go the menu: Process -> Properties Then do this: 1) Click the category 'Synthesis Options' 2) Now, near the bottom-right of the window, change 'Property display level' -> Advanced 3) Inside the 'Property Name' scroll-box, look for table-entry "Verilog...
  10. M

    RISC Processor design

    ARM isn't open-source -- it's owned by the company ARM Ltd. You can download and use nnARM for personal-use and academic study. But you would be very foolish to build commercial project around an unauthorized project like nnARM. There are several open-source MIPS-clones that are good for...
  11. M

    What are the diffrent types of Synthesis Tools

    How? Design Compiler support Systemverilog for synthesis. None of Cadence's front-end design-tools support Systemverilog. (I don't include Cadence Incisive/NCsim, since that is a simulation and not a design tool.) Altera Quartus-II already supports Systemverilog, though not nearly as complete...
  12. M

    What are the typical costs of EDA tools?

    Re: Costs of EDA Tools The case you're talking about is a third-party (not the EDA-vendor) trying to rent out EDA license-time. All EDA-vendors forbid a third-party from reselling a license. Otherwise every university would buy the $4500/yr "all-you-can-eat" license, and rent out to...
  13. M

    What is Clock Reconvergence?

    reconverging Depends on the context... In static-timing-analysis, clock-reconvergence describes the situation where you perform multi-corner (best-case, worst-case) analysis. For a timing-path in your design, there are two important flops: driving-flop and capture-flop. If these two share...
  14. M

    VHDL "subtype range" in Systemverilog?

    localparam in vhdl signal my_sig1, my_sig2 : natural range 0 to INIT_CYCLES; -- I want to port some VHDL RTL files to Systemverilog (for synthesis.) There are a few VHDL subtype-declarations I don't know how to write (directly) in Systemverilog: positive, negative, natural Now, I know i can...
  15. M

    The comparison of ARM and MIPS?

    Re: ARM or MIPS? ARM was famous for the best overall performance to power-consumption ratio. The "Thumb" mode (16-bit instruction words) also reduced codesize. Both these features together helped ARM dominate the portable-electronics market. Today, ARM proessor is de-facto standard of...

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