What are the diffrent types of Synthesis Tools

[gbaerf]

Hi,

Pls tell me name of different synthesis tools available in the market and which area they are basically strong in to ???
I know Synplicity tools are best for FPGA and CPLD based synthesis ...
and From mentor Graphics the tool is precesion.

I want to know the other tools ...

regards/gbaerf

 

[vak]

Design Complier from synopsys , Blast Create from Magma , Cadence also has one - RTL complier ( Not sure about the name, but this tool is from Get2Chip ) - on the ASIC front.

 

[leongch]

RTL COMPILER ppl normally call it RC ..

 

[deh_fuhrer]

leanardo spectrum precision rtl synthesis for FPGA...

 

[spauls]

DC , RC and Blast RTL

 

[gbaerf]

hellow Vak,

what did u mean by " ( Not sure about the name, but this tool is from Get2Chip ) - on the ASIC front. ) "
can you please explain a little more.

regards,

 

[Adam.Yakuvitz]

All the Synthesis Tools (ASIC & FPGA) in the world ranked by popularity

ASIC Tools
- Synopsys Design Compiler
- Cadence RTL Compiler (from Get2Chip Acquisition)
- Magma Blast RTL
- Cadence BuildGates (from Ambit Acquisition)
- Synplicity's - Synplify ASIC
- Incentia DesignCraft

FPGA Tools
- Synplicity's SynplifyPro
- Mentor Leonardo Spectrum Precision
- Synopsys FPGA Express II (May be Dead)
- Xilinx Synthesis (free)
- Altera Synthesis (free)

 

[boardlanguage]

FPGA Tools
...
- Synopsys FPGA Express II (May be Dead)
...

Synopsys renamed the product to 'FPGA Compiler', to make it sound more familiar with Design Compiler.

Cadence also had Ambit Buildgates (part of PKS5, which is still bundled with SOC Encounter, for some reason.) But you can't get a new licesnse for Ambit/PKS5 anymore, Cadence no longer supports it and steers everyone toward RTL Compiler.

 

[aravind]

Get2chip is old name before cadence acquisation.

After cadence bought it name changed as RTLC (RTL compiler) or RC

Now RC is performing better than DC

 

[modelsim62c]

Get2chip is old name before cadence acquisation.
After cadence bought it name changed as RTLC (RTL compiler) or RC
Now RC is performing better than DC

How?
Design Compiler support Systemverilog for synthesis. None of Cadence's front-end design-tools support Systemverilog. (I don't include Cadence Incisive/NCsim, since that is a simulation and not a design tool.)

Altera Quartus-II already supports Systemverilog, though not nearly as complete as Design Compiler. Xilinx Foundation/Webpack ISE will start supporting Systemverilog in version 10 (early next year.)