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Recent content by minho_ha

  1. M

    Synopsys DC power report meaning

    I have a one more question. In power report using DC, this report shows average(or some middle range value) power consumption?? not worst case??
  2. M

    Synopsys DC power report meaning

    You help me a lot!! Thanks!
  3. M

    Synopsys DC power report meaning

    Is "switching power" considering switching activity??
  4. M

    Synopsys DC power report meaning

    Hi. I made a small module and got post-synthesis reports including timing, area, power etc. In power report, is it show that average power dissipation including switching activity??
  5. M

    Using Synopsys DC, power report problem

    I'm trying to get power consumption report using Synopsys DC. When I compiled my verilog file before, power report was fine. But, today, I compiled same verilog file again, power report is strange. Switching power accounts for more than 95% of dynamic power. Before that, the switching power...
  6. M

    Using the Xilinx Memory Endpoint Test (MET), how can I change the start address??

    I just wanna get advice from the one who used MET driver before.
  7. M

    Using the Xilinx Memory Endpoint Test (MET), how can I change the start address??

    Hi, I'm trying to use MET driver for checking the signal between host PC (linux OS, ubuntu) and FPGA BRAM. System is consist of 'PCIe - AXI - BRAM controller - BRAM'. (All IPs are presented by Xilinx Vivado) I succeeded in changing the data when read and write. And now, I wanna change the...
  8. M

    Is it possible to debug DDR memory using ILA core?? (Xilinx board)

    I want to check the address transition between AXI and DDR4 memory.
  9. M

    Is it possible to debug DDR memory using ILA core?? (Xilinx board)

    If I add buffer or register after ddr4 ram, can I debug between ddr4 ram and buffer (or register)?
  10. M

    Is it possible to debug DDR memory using ILA core?? (Xilinx board)

    I use Xilinx MET driver (xapp1022). Using that driver, I wrote data from PC -> PCIe -> AXI -> MIG. I can debug from PCIe to AXI, from AXI to MIG. I want to see the after MIG.
  11. M

    Is it possible to debug DDR memory using ILA core?? (Xilinx board)

    Hi. I have a problem with the use of ILA core. I am attempting to debug a system configured with 'PCIe-AXI-MIG' using ILA core. At this time, AXI can be debugged with ILA core, but DDR memory cannot be debugged. Especially, I want to see the address of DDR memory. (c0_ddr4_adr signal) When I...
  12. M

    what is 'warm reset (or rebooting)' of FPGA?

    How can I warm-reboot FPGA?? Is there any button or instruction??
  13. M

    what is 'warm reset (or rebooting)' of FPGA?

    I followed xilinx tutorial 'xtp350-kcu105-pcie-c-2016-1.pdf'. In that tutorial, there is a term called 'warm-reset'. I know warm-reboot in computer, which use 'ctrl+alt+del'. How can I do 'warm-reset' in FPGA?? When I programed PCIe core into KCU105 evaluation board, linux PC cannot...
  14. M

    Using a FPGA board as storage

    Thanks a lot. I add PCIe integrated core in FPGA. But, in PC side, there is no driver what you mentioned. I just guess that if i allocate BRAM in FPGA, it is similar to HDD and just need mount process. But when i use 'fdisk', there is no FPGA storage what i want. Anyway, you're answer help me...
  15. M

    Using a FPGA board as storage

    Of course i will generate the bitstream and program it. After that should i mount FPGA board like HDD?? Or is there any other method to mount the FPGA board??
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