minho_ha
Junior Member level 3
Hi.
I have a problem with the use of ILA core.
I am attempting to debug a system configured with 'PCIe-AXI-MIG' using ILA core.
At this time, AXI can be debugged with ILA core, but DDR memory cannot be debugged. Especially, I want to see the address of DDR memory. (c0_ddr4_adr signal)
When I opened 'Synthesized Design', Vivado show this message "[Chipscope 16-3] Cannot debug net 'design_1_i/ddr4_0_C0_DDR4_ADR[0]'; it is not accessible from the fabric routing." Other port are same.
Is it impossible to see the address of DDR memory using ILA core?
Please answer.
I have a problem with the use of ILA core.
I am attempting to debug a system configured with 'PCIe-AXI-MIG' using ILA core.
At this time, AXI can be debugged with ILA core, but DDR memory cannot be debugged. Especially, I want to see the address of DDR memory. (c0_ddr4_adr signal)
When I opened 'Synthesized Design', Vivado show this message "[Chipscope 16-3] Cannot debug net 'design_1_i/ddr4_0_C0_DDR4_ADR[0]'; it is not accessible from the fabric routing." Other port are same.
Is it impossible to see the address of DDR memory using ILA core?
Please answer.