what is 'warm reset (or rebooting)' of FPGA?

[minho_ha]

I followed xilinx tutorial 'xtp350-kcu105-pcie-c-2016-1.pdf'.

In that tutorial, there is a term called 'warm-reset'.

I know warm-reboot in computer, which use 'ctrl+alt+del'.

How can I do 'warm-reset' in FPGA??

When I programed PCIe core into KCU105 evaluation board, linux PC cannot recognize PCIe core. But, when I turned off PC, while FPGA board was still turned on, and reboot the PC, and then linux PC can recognize PCIe core.

Is this rebooting method 'warm-reset'??

 

[srizbf]

warm-reset and warm-booting of PC are similar.

That is starting the execution or opeartion of the system by bypassing certain internal routines.

On the otherhand , cold-reset(or booting) is the power-on sequence.

 

[minho_ha]

warm-reset and warm-booting of PC are similar.

That is starting the execution or opeartion of the system by bypassing certain internal routines.

On the otherhand , cold-reset(or booting) is the power-on sequence.

How can I warm-reboot FPGA?? Is there any button or instruction??

 

[dpaul]

How can I warm-reboot FPGA?? Is there any button or instruction??

Do you see any push-button switch named reset or cpu_reset on the FPGA dev board (generally near the power switch)?
If yes, try pressing that (after you have the bit-stream downloaded) when the board and PC are powered on. It might give you the desired effect.
My answer is just a guess!

 

[srizbf]

There seems to be no such thing in the evaluation board.
And , no warm-reset reference in the pdf manual.

Are you referring the warm-reset with respect to PC or the pcie-evaluation board?
the only switch available is cpu-reset in the board.

 

[ads-ee]

the difference between the warm-reset of hardware and the cold-boot is that cold-boot is from power applied to the hardare and warm-reset is using whatever reset capability was designed into the hardware to re-set the hardware to a known state. This may be done using a CPU initiated reset (a register containing a reset signal), a hardware reset pin (system reset), or perhaps both in the same design.

A PCIe evaluation board should have a reset that comes in from PCIe that should likely be a source for a warm-reset signal when in a PCIe system.

 

[FvM]

Loading the configuration into the FPGA will completely "reboot" it. Problem is that the Linux OS must be instructed to rescan the PCIe bus after configuring the FPGA. I guess, the problem exists only during test and debugging. In regular operation, the configuration will be loaded from flash memory before the OS enumerates the PCIe devices.

 

[ads-ee]

Loading the configuration into the FPGA will completely "reboot" it. Problem is that the Linux OS must be instructed to rescan the PCIe bus after configuring the FPGA. I guess, the problem exists only during test and debugging. In regular operation, the configuration will be loaded from flash memory before the OS enumerates the PCIe devices.

This is a great point. As this is a ultrascale Kintex part if you load the entire configuration bit file for the entire design it may take quite a while even if compressed (perhaps violating the PCIe specs).

I've seen some app notes on using partial reconfiguration to only program the PCIe logic (much smaller bit file) that will allow the PCIe design to be up and running in a timely fashion so it can be enumerated by the OS, the PCIe design loaded has the capability of accepting commands to load the partial reconfiguration bit streams that implement the functional logic that is not part of the PCIe design without reprogramming the PCIe logic.